feat: implement WRAM

src/core/nds7/Bus.zig

@@ -4,6 +4,7 @@ const io = @import("io.zig");
 const Scheduler = @import("../Scheduler.zig");
 const SharedIo = @import("../io.zig").Io;
 const SharedContext = @import("../emu.zig").SharedContext;
+const Wram = @import("../emu.zig").Wram;
 const forceAlign = @import("../emu.zig").forceAlign;
 
 const Allocator = std.mem.Allocator;
@@ -16,6 +17,7 @@ const log = std.log.scoped(.nds7_bus);
 
 scheduler: *Scheduler,
 main: *[4 * MiB]u8,
+wram_shr: *Wram,
 wram: *[64 * KiB]u8,
 io: io.Io,
 
@@ -26,6 +28,7 @@ pub fn init(allocator: Allocator, scheduler: *Scheduler, shared_ctx: SharedConte
 
     return .{
         .main = shared_ctx.main,
+        .wram_shr = shared_ctx.wram,
         .wram = wram,
         .scheduler = scheduler,
         .io = io.Io.init(shared_ctx.io),
@@ -60,6 +63,10 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
 
     return switch (aligned_addr) {
         0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
+        0x0300_0000...0x037F_FFFF => switch (self.io.shared.wramcnt.mode.read()) {
+            0b00 => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
+            else => self.wram_shr.read(T, .nds7, address & 0x7FFF),
+        },
         0x0380_0000...0x0380_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
         0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
         else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
@@ -88,6 +95,10 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
 
     switch (aligned_addr) {
         0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
+        0x0300_0000...0x037F_FFFF => switch (self.io.shared.wramcnt.mode.read()) {
+            0b00 => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
+            else => self.wram_shr.write(T, .nds7, address & 0x7FFF, value),
+        },
         0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
         0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
         else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),

src/core/nds7/io.zig

@@ -33,6 +33,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
             else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
         },
         u8 => switch (address) {
+            0x0400_0241 => bus.io.shared.wramcnt.raw,
             else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
         },
         else => @compileError(T ++ " is an unsupported bus read type"),