feat(io): implement ipcsync (non-irq) and ipcfifo (non-irq)
This commit is contained in:
parent
2484f634d8
commit
eba2de39fb
228
src/core/io.zig
228
src/core/io.zig
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@ -5,6 +5,10 @@ const Bit = @import("bitfield").Bit;
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const log = std.log.scoped(.shared_io);
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// FIXME: This whole thing is bad bad bad bad bad
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// I think only the IPC stuff needs to be here, since they talk to each other.
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// every other "shared I/O register" is just duplicated on both CPUs. So they shouldn't be here
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pub const Io = struct {
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/// Interrupt Master Enable
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/// Read/Write
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@ -39,120 +43,130 @@ fn warn(comptime format: []const u8, args: anytype) u0 {
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return 0;
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}
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// TODO: Please Rename
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// TODO: Figure out a way to apply masks while calling valueAtAddressOffset
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// TODO: These aren't optimized well. Can we improve that?
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pub inline fn valueAtAddressOffset(comptime T: type, address: u32, value: T) u8 {
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const L2I = std.math.Log2Int(T);
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return @truncate(switch (T) {
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u16 => value >> @as(L2I, @truncate((address & 1) << 3)),
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u32 => value >> @as(L2I, @truncate((address & 3) << 3)),
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else => @compileError("unsupported for " ++ @typeName(T) ++ "values"),
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});
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}
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fn WriteOption(comptime T: type) type {
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return struct { mask: ?T = null };
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}
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// TODO: also please rename
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// TODO: Figure out a way to apply masks while calling writeToAddressOffset
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// TODO: These aren't optimized well. Can we improve that?
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pub inline fn writeToAddressOffset(
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register: anytype,
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address: u32,
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value: anytype,
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// mask: WriteOption(@typeInfo(@TypeOf(register)).Pointer.child),
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) void {
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const Ptr = @TypeOf(register);
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const ChildT = @typeInfo(Ptr).Pointer.child;
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const ValueT = @TypeOf(value);
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const left = register.*;
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register.* = switch (ChildT) {
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u32 => switch (ValueT) {
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u16 => blk: {
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// TODO: This probably gets deleted
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const offset: u1 = @truncate(address >> 1);
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break :blk switch (offset) {
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0b0 => (left & 0xFFFF_0000) | value,
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0b1 => (left & 0x0000_FFFF) | @as(u32, value) << 16,
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};
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},
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u8 => blk: {
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// TODO: Remove branching
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const offset: u2 = @truncate(address);
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break :blk switch (offset) {
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0b00 => (left & 0xFFFF_FF00) | value,
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0b01 => (left & 0xFFFF_00FF) | @as(u32, value) << 8,
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0b10 => (left & 0xFF00_FFFF) | @as(u32, value) << 16,
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0b11 => (left & 0x00FF_FFFF) | @as(u32, value) << 24,
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};
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},
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else => @compileError("for " ++ @typeName(Ptr) ++ ", T must be u16 or u8"),
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},
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u16 => blk: {
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if (ValueT != u8) @compileError("for " ++ @typeName(Ptr) ++ ", T must be u8");
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const shamt = @as(u4, @truncate(address & 1)) << 3;
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const mask: u16 = 0xFF00 >> shamt;
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const value_shifted = @as(u16, value) << shamt;
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break :blk (left & mask) | value_shifted;
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},
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else => @compileError("unsupported for " ++ @typeName(Ptr) ++ " values"),
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};
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}
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const IpcFifo = struct {
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const Sync = IpcSync;
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const Control = IpcFifoCnt;
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/// IPC Synchronize
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_nds7: Impl = .{},
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_nds9: Impl = .{},
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const Source = enum { nds7, nds9 };
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const Impl = struct {
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/// IPC Synchronize
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/// Read/Write
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sync: Sync = .{ .raw = 0x0000_0000 },
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/// IPC Fifo Control
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/// Read/Write
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cnt: Control = .{ .raw = 0x0000_0101 },
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fifo: Fifo = Fifo{},
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/// Latch containing thel last read value from a FIFO
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last_read: ?u32 = null,
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};
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/// IPCSYNC
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/// Read/Write
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sync: Sync = .{ .raw = 0x0000_0000 },
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pub fn setIpcSync(self: *@This(), comptime src: Source, value: anytype) void {
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switch (src) {
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.nds7 => {
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self._nds7.sync.raw = masks.ipcFifoSync(self._nds7.sync.raw, value);
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self._nds9.sync.raw = masks.mask(self._nds9.sync.raw, (self._nds7.sync.raw >> 8) & 0xF, 0xF);
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},
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.nds9 => {
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self._nds9.sync.raw = masks.ipcFifoSync(self._nds9.sync.raw, value);
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self._nds7.sync.raw = masks.mask(self._nds7.sync.raw, (self._nds9.sync.raw >> 8) & 0xF, 0xF);
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},
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}
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}
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/// IPC Fifo Control
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/// IPCFIFOCNT
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/// Read/Write
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cnt: Control = .{ .raw = 0x0000_0000 },
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fifo: [2]Fifo = .{ Fifo{}, Fifo{} },
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const Source = enum { arm7, arm9 };
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pub fn setIpcFifoCnt(self: *@This(), comptime src: Source, value: anytype) void {
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switch (src) {
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.nds7 => self._nds7.cnt.raw = masks.ipcFifoCnt(self._nds7.cnt.raw, value),
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.nds9 => self._nds9.cnt.raw = masks.ipcFifoCnt(self._nds9.cnt.raw, value),
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}
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}
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/// IPC Send FIFO
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/// Write-Only
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pub fn send(self: *@This(), comptime src: Source, value: u32) !void {
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const idx = switch (src) {
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.arm7 => 0,
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.arm9 => 1,
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};
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switch (src) {
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.nds7 => {
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if (!self._nds7.cnt.enable_fifos.read()) return;
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try self._nds7.fifo.push(value);
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if (!self.cnt.enable_fifos.read()) return;
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// update status bits
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self._nds7.cnt.send_fifo_empty.write(self._nds7.fifo._len() == 0);
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self._nds9.cnt.recv_fifo_empty.write(self._nds7.fifo._len() == 0);
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try self.fifo[idx].push(value);
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self._nds7.cnt.send_fifo_full.write(self._nds7.fifo._len() == 0x10);
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self._nds9.cnt.recv_fifo_full.write(self._nds7.fifo._len() == 0x10);
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},
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.nds9 => {
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if (!self._nds9.cnt.enable_fifos.read()) return;
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try self._nds9.fifo.push(value);
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// update status bits
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self._nds9.cnt.send_fifo_empty.write(self._nds9.fifo._len() == 0);
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self._nds7.cnt.recv_fifo_empty.write(self._nds9.fifo._len() == 0);
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self._nds9.cnt.send_fifo_full.write(self._nds9.fifo._len() == 0x10);
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self._nds7.cnt.recv_fifo_full.write(self._nds9.fifo._len() == 0x10);
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},
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}
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}
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/// IPC Receive FIFO
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/// Read-Only
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pub fn recv(self: *@This(), comptime src: Source) u32 {
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const idx = switch (src) {
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.arm7 => 1, // switched around on purpose
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.arm9 => 0,
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};
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switch (src) {
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.nds7 => {
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const enabled = self._nds7.cnt.enable_fifos.read();
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const val_opt = if (enabled) self._nds9.fifo.pop() else self._nds9.fifo.peek();
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const enabled = self.cnt.enable_fifos.read();
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const val_opt = if (enabled) self.fifo[idx].pop() else self.fifo[idx].peek();
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const value = if (val_opt) |val| blk: {
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self._nds9.last_read = val;
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break :blk val;
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} else blk: {
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self._nds7.cnt.fifo_error.set();
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break :blk self._nds7.last_read orelse 0x0000_0000;
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};
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return val_opt orelse blk: {
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self.cnt.send_fifo_empty.set();
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// update status bits
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self._nds7.cnt.recv_fifo_empty.write(self._nds9.fifo._len() == 0);
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self._nds9.cnt.send_fifo_empty.write(self._nds9.fifo._len() == 0);
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break :blk 0x0000_0000;
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};
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self._nds7.cnt.recv_fifo_full.write(self._nds9.fifo._len() == 0x10);
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self._nds9.cnt.send_fifo_full.write(self._nds9.fifo._len() == 0x10);
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return value;
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},
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.nds9 => {
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const enabled = self._nds9.cnt.enable_fifos.read();
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const val_opt = if (enabled) self._nds7.fifo.pop() else self._nds7.fifo.peek();
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const value = if (val_opt) |val| blk: {
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self._nds7.last_read = val;
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break :blk val;
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} else blk: {
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self._nds9.cnt.fifo_error.set();
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break :blk self._nds7.last_read orelse 0x0000_0000;
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};
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// update status bits
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self._nds9.cnt.recv_fifo_empty.write(self._nds7.fifo._len() == 0);
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self._nds7.cnt.send_fifo_empty.write(self._nds7.fifo._len() == 0);
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self._nds9.cnt.recv_fifo_full.write(self._nds7.fifo._len() == 0x10);
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self._nds7.cnt.send_fifo_full.write(self._nds7.fifo._len() == 0x10);
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return value;
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},
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}
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}
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};
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@ -208,32 +222,26 @@ pub const masks = struct {
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const Bus9 = @import("nds9/Bus.zig");
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const Bus7 = @import("nds7/Bus.zig");
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pub inline fn ipcFifoSync(bus: anytype, value: anytype) @TypeOf(value) {
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comptime verifyBusType(@TypeOf(bus));
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const T = @TypeOf(value);
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const _mask: T = 0xF;
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return value & ~_mask | @as(T, @intCast(bus.io.shared.ipc_fifo.sync.raw & _mask));
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inline fn ipcFifoSync(sync: u32, value: anytype) u32 {
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const _mask: u32 = 0x6F00;
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return (@as(u32, value) & _mask) | (sync & ~_mask);
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}
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pub inline fn ipcFifoCnt(bus: anytype, value: anytype) @TypeOf(value) {
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comptime verifyBusType(@TypeOf(bus));
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const T = @TypeOf(value);
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const _mask: T = 0x0303;
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inline fn ipcFifoCnt(cnt: u32, value: anytype) u32 {
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const _mask: u32 = 0xC40C;
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const err_mask: u32 = 0x4000; // bit 14
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return value & ~_mask | @as(T, @intCast(bus.io.shared.ipc_fifo.cnt.raw & _mask));
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const err_bit = (cnt & err_mask) & ~(value & err_mask);
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if (value & 0b1000 != 0) log.err("TODO: handle IPCFIFOCNT.3", .{});
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const without_err = (@as(u32, value) & _mask) | (cnt & ~_mask);
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return (without_err & ~err_mask) | err_bit;
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}
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/// General Mask helper
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pub inline fn mask(original: anytype, value: @TypeOf(original), _mask: @TypeOf(original)) @TypeOf(original) {
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return (value & _mask) | (original & ~_mask);
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}
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fn verifyBusType(comptime BusT: type) void {
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std.debug.assert(@typeInfo(BusT) == .Pointer);
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std.debug.assert(@typeInfo(BusT).Pointer.size == .One);
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std.debug.assert(@typeInfo(BusT).Pointer.child == Bus9 or @typeInfo(BusT).Pointer.child == Bus7);
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}
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};
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pub const nds7 = struct {
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@ -24,12 +24,12 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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0x0400_0210 => bus.io.shared.ie,
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0x0400_0214 => bus.io.shared.irq,
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0x0410_0000 => bus.io.shared.ipc_fifo.recv(.arm7),
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0x0410_0000 => bus.io.shared.ipc_fifo.recv(.nds7),
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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},
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u16 => switch (address) {
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0x0400_0180 => @truncate(bus.io.shared.ipc_fifo.sync.raw),
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0x0400_0184 => @truncate(bus.io.shared.ipc_fifo.cnt.raw),
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0x0400_0180 => @truncate(bus.io.shared.ipc_fifo._nds7.sync.raw),
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0x0400_0184 => @truncate(bus.io.shared.ipc_fifo._nds7.cnt.raw),
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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},
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u8 => switch (address) {
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@ -46,12 +46,12 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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0x0400_0210 => bus.io.shared.ie = value,
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0x0400_0214 => bus.io.shared.irq = value,
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0x0400_0188 => bus.io.shared.ipc_fifo.send(.arm7, value) catch |e| std.debug.panic("FIFO error: {}", .{e}),
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0x0400_0188 => bus.io.shared.ipc_fifo.send(.nds7, value) catch |e| std.debug.panic("FIFO error: {}", .{e}),
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else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
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},
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u16 => switch (address) {
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0x0400_0180 => bus.io.shared.ipc_fifo.sync.raw = masks.ipcFifoSync(bus, value),
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0x0400_0184 => bus.io.shared.ipc_fifo.cnt.raw = masks.ipcFifoCnt(bus, value),
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0x0400_0180 => bus.io.shared.ipc_fifo.setIpcSync(.nds7, value),
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0x0400_0184 => bus.io.shared.ipc_fifo.setIpcFifoCnt(.nds7, value),
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else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
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},
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u8 => switch (address) {
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@ -43,15 +43,15 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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0x0400_02AC => @truncate(bus.io.div.remainder >> 32),
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0x0400_02B4 => @truncate(bus.io.sqrt.result),
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0x0410_0000 => bus.io.shared.ipc_fifo.recv(.arm9),
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0x0410_0000 => bus.io.shared.ipc_fifo.recv(.nds9),
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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},
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u16 => switch (address) {
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0x0400_0004 => bus.ppu.io.dispstat.raw,
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0x0400_0130 => bus.io.keyinput.load(.Monotonic),
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0x0400_0180 => @truncate(bus.io.shared.ipc_fifo.sync.raw),
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0x0400_0184 => @truncate(bus.io.shared.ipc_fifo.cnt.raw),
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0x0400_0180 => @truncate(bus.io.shared.ipc_fifo._nds9.sync.raw),
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0x0400_0184 => @truncate(bus.io.shared.ipc_fifo._nds9.cnt.raw),
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0x0400_0280 => @truncate(bus.io.div.cnt.raw),
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0x0400_02B0 => @truncate(bus.io.sqrt.cnt.raw),
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@ -69,9 +69,9 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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switch (T) {
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u32 => switch (address) {
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0x0400_0000 => bus.ppu.io.dispcnt_a.raw = value,
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0x0400_0180 => bus.io.shared.ipc_fifo.sync.raw = masks.ipcFifoSync(bus, value),
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0x0400_0184 => bus.io.shared.ipc_fifo.cnt.raw = masks.ipcFifoCnt(bus, value),
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0x0400_0188 => bus.io.shared.ipc_fifo.send(.arm9, value) catch |e| std.debug.panic("IPC FIFO Error: {}", .{e}),
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0x0400_0180 => bus.io.shared.ipc_fifo.setIpcSync(.nds9, value),
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0x0400_0184 => bus.io.shared.ipc_fifo.setIpcFifoCnt(.nds9, value),
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0x0400_0188 => bus.io.shared.ipc_fifo.send(.nds9, value) catch |e| std.debug.panic("IPC FIFO Error: {}", .{e}),
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0x0400_0240 => {
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bus.ppu.io.vramcnt_a.raw = @truncate(value >> 0); // 0x0400_0240
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@ -114,8 +114,8 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
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},
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u16 => switch (address) {
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0x0400_0180 => bus.io.shared.ipc_fifo.sync.raw = masks.ipcFifoSync(bus, value),
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0x0400_0184 => bus.io.shared.ipc_fifo.cnt.raw = masks.ipcFifoCnt(bus, value),
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0x0400_0180 => bus.io.shared.ipc_fifo.setIpcSync(.nds9, value),
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0x0400_0184 => bus.io.shared.ipc_fifo.setIpcFifoCnt(.nds9, value),
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0x0400_0208 => bus.io.shared.ime = value & 1 == 1,
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0x0400_0280 => {
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