feat: implement (?) nds7 dma transfer controllers
This commit is contained in:
parent
e0171e5b65
commit
ea63b04056
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@ -5,6 +5,8 @@ const Scheduler = @import("Scheduler.zig");
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const Allocator = std.mem.Allocator;
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const dma7 = @import("nds7/dma.zig");
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/// Load a NDS Cartridge
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///
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/// intended to be used immediately after Emulator initialization
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@ -115,8 +117,9 @@ pub fn runFrame(scheduler: *Scheduler, system: System) void {
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system.arm946es.step();
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}
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if (comptime halt != .arm7)
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if (!dma7.step(system.arm7tdmi) and comptime halt != .arm7) {
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system.arm7tdmi.step();
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}
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},
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}
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@ -325,6 +325,11 @@ pub const IntEnable = extern union {
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hblank: Bit(u32, 1),
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coincidence: Bit(u32, 2),
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dma0: Bit(u32, 8),
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dma1: Bit(u32, 9),
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dma2: Bit(u32, 10),
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dma3: Bit(u32, 11),
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ipcsync: Bit(u32, 16),
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ipc_send_empty: Bit(u32, 17),
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ipc_recv_not_empty: Bit(u32, 18),
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@ -8,6 +8,8 @@ const Vram = @import("../ppu/Vram.zig");
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const Bios = @import("Bios.zig");
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const forceAlign = @import("../emu.zig").forceAlign;
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const Controllers = @import("dma.zig").Controllers;
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const Allocator = std.mem.Allocator;
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const Mode = enum { normal, debug };
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@ -22,6 +24,8 @@ shr_wram: *Wram,
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wram: *[64 * KiB]u8,
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vram: *Vram,
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dma: Controllers = .{},
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io: io.Io,
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bios: Bios,
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@ -0,0 +1,364 @@
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const std = @import("std");
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const System = @import("../emu.zig").System;
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const DmaCnt = @import("io.zig").DmaCnt;
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const rotr = std.math.rotr;
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const shift = @import("../../util.zig").shift;
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const subset = @import("../../util.zig").subset;
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const handleInterrupt = @import("../emu.zig").handleInterrupt;
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const log = std.log.scoped(.nds7_dma_transfer);
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pub const Controllers = struct {
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Controller(0) = Controller(0){},
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Controller(1) = Controller(1){},
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Controller(2) = Controller(2){},
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Controller(3) = Controller(3){},
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};
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pub fn read(comptime T: type, dma: *const Controllers, addr: u32) ?T {
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const byte_addr: u8 = @truncate(addr);
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return switch (T) {
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u32 => switch (byte_addr) {
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0xB0, 0xB4 => null, // DMA0SAD, DMA0DAD,
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0xB8 => @as(T, dma.*[0].dmacntH()) << 16, // DMA0CNT_L is write-only
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0xBC, 0xC0 => null, // DMA1SAD, DMA1DAD
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0xC4 => @as(T, dma.*[1].dmacntH()) << 16, // DMA1CNT_L is write-only
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0xC8, 0xCC => null, // DMA2SAD, DMA2DAD
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0xD0 => @as(T, dma.*[2].dmacntH()) << 16, // DMA2CNT_L is write-only
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0xD4, 0xD8 => null, // DMA3SAD, DMA3DAD
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0xDC => @as(T, dma.*[3].dmacntH()) << 16, // DMA3CNT_L is write-only
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else => warn("unaligned {} read from 0x{X:0>8}", .{ T, addr }),
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},
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u16 => switch (byte_addr) {
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0xB0, 0xB2, 0xB4, 0xB6 => null, // DMA0SAD, DMA0DAD
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0xB8 => 0x0000, // DMA0CNT_L, suite.gba expects 0x0000 instead of 0xDEAD
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0xBA => dma.*[0].dmacntH(),
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0xBC, 0xBE, 0xC0, 0xC2 => null, // DMA1SAD, DMA1DAD
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0xC4 => 0x0000, // DMA1CNT_L
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0xC6 => dma.*[1].dmacntH(),
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0xC8, 0xCA, 0xCC, 0xCE => null, // DMA2SAD, DMA2DAD
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0xD0 => 0x0000, // DMA2CNT_L
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0xD2 => dma.*[2].dmacntH(),
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0xD4, 0xD6, 0xD8, 0xDA => null, // DMA3SAD, DMA3DAD
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0xDC => 0x0000, // DMA3CNT_L
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0xDE => dma.*[3].dmacntH(),
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else => warn("unaligned {} read from 0x{X:0>8}", .{ T, addr }),
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},
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u8 => switch (byte_addr) {
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0xB0...0xB7 => null, // DMA0SAD, DMA0DAD
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0xB8, 0xB9 => 0x00, // DMA0CNT_L
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0xBA, 0xBB => @truncate(dma.*[0].dmacntH() >> shift(u16, byte_addr)),
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0xBC...0xC3 => null, // DMA1SAD, DMA1DAD
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0xC4, 0xC5 => 0x00, // DMA1CNT_L
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0xC6, 0xC7 => @truncate(dma.*[1].dmacntH() >> shift(u16, byte_addr)),
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0xC8...0xCF => null, // DMA2SAD, DMA2DAD
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0xD0, 0xD1 => 0x00, // DMA2CNT_L
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0xD2, 0xD3 => @truncate(dma.*[2].dmacntH() >> shift(u16, byte_addr)),
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0xD4...0xDB => null, // DMA3SAD, DMA3DAD
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0xDC, 0xDD => 0x00, // DMA3CNT_L
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0xDE, 0xDF => @truncate(dma.*[3].dmacntH() >> shift(u16, byte_addr)),
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else => warn("unexpected {} read from 0x{X:0>8}", .{ T, addr }),
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},
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else => @compileError("DMA: Unsupported read width"),
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};
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}
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pub fn write(comptime T: type, dma: *Controllers, addr: u32, value: T) void {
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const byte_addr: u8 = @truncate(addr);
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switch (T) {
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u32 => switch (byte_addr) {
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0xB0 => dma.*[0].setDmasad(value),
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0xB4 => dma.*[0].setDmadad(value),
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0xB8 => dma.*[0].setDmacnt(value),
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0xBC => dma.*[1].setDmasad(value),
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0xC0 => dma.*[1].setDmadad(value),
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0xC4 => dma.*[1].setDmacnt(value),
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0xC8 => dma.*[2].setDmasad(value),
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0xCC => dma.*[2].setDmadad(value),
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0xD0 => dma.*[2].setDmacnt(value),
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0xD4 => dma.*[3].setDmasad(value),
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0xD8 => dma.*[3].setDmadad(value),
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0xDC => dma.*[3].setDmacnt(value),
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else => log.warn("Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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u16 => switch (byte_addr) {
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0xB0, 0xB2 => dma.*[0].setDmasad(subset(u32, u16, byte_addr, dma.*[0].sad, value)),
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0xB4, 0xB6 => dma.*[0].setDmadad(subset(u32, u16, byte_addr, dma.*[0].dad, value)),
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0xB8 => dma.*[0].setDmacntL(value),
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0xBA => dma.*[0].setDmacntH(value),
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0xBC, 0xBE => dma.*[1].setDmasad(subset(u32, u16, byte_addr, dma.*[1].sad, value)),
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0xC0, 0xC2 => dma.*[1].setDmadad(subset(u32, u16, byte_addr, dma.*[1].dad, value)),
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0xC4 => dma.*[1].setDmacntL(value),
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0xC6 => dma.*[1].setDmacntH(value),
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0xC8, 0xCA => dma.*[2].setDmasad(subset(u32, u16, byte_addr, dma.*[2].sad, value)),
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0xCC, 0xCE => dma.*[2].setDmadad(subset(u32, u16, byte_addr, dma.*[2].dad, value)),
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0xD0 => dma.*[2].setDmacntL(value),
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0xD2 => dma.*[2].setDmacntH(value),
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0xD4, 0xD6 => dma.*[3].setDmasad(subset(u32, u16, byte_addr, dma.*[3].sad, value)),
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0xD8, 0xDA => dma.*[3].setDmadad(subset(u32, u16, byte_addr, dma.*[3].dad, value)),
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0xDC => dma.*[3].setDmacntL(value),
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0xDE => dma.*[3].setDmacntH(value),
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else => log.warn("Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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u8 => switch (byte_addr) {
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0xB0, 0xB1, 0xB2, 0xB3 => dma.*[0].setDmasad(subset(u32, u8, byte_addr, dma.*[0].sad, value)),
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0xB4, 0xB5, 0xB6, 0xB7 => dma.*[0].setDmadad(subset(u32, u8, byte_addr, dma.*[0].dad, value)),
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0xB8, 0xB9 => dma.*[0].setDmacntL(subset(u16, u8, byte_addr, dma.*[0].word_count, value)),
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0xBA, 0xBB => dma.*[0].setDmacntH(subset(u16, u8, byte_addr, dma.*[0].cnt.raw, value)),
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0xBC, 0xBD, 0xBE, 0xBF => dma.*[1].setDmasad(subset(u32, u8, byte_addr, dma.*[1].sad, value)),
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0xC0, 0xC1, 0xC2, 0xC3 => dma.*[1].setDmadad(subset(u32, u8, byte_addr, dma.*[1].dad, value)),
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0xC4, 0xC5 => dma.*[1].setDmacntL(subset(u16, u8, byte_addr, dma.*[1].word_count, value)),
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0xC6, 0xC7 => dma.*[1].setDmacntH(subset(u16, u8, byte_addr, dma.*[1].cnt.raw, value)),
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0xC8, 0xC9, 0xCA, 0xCB => dma.*[2].setDmasad(subset(u32, u8, byte_addr, dma.*[2].sad, value)),
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0xCC, 0xCD, 0xCE, 0xCF => dma.*[2].setDmadad(subset(u32, u8, byte_addr, dma.*[2].dad, value)),
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0xD0, 0xD1 => dma.*[2].setDmacntL(subset(u16, u8, byte_addr, dma.*[2].word_count, value)),
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0xD2, 0xD3 => dma.*[2].setDmacntH(subset(u16, u8, byte_addr, dma.*[2].cnt.raw, value)),
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0xD4, 0xD5, 0xD6, 0xD7 => dma.*[3].setDmasad(subset(u32, u8, byte_addr, dma.*[3].sad, value)),
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0xD8, 0xD9, 0xDA, 0xDB => dma.*[3].setDmadad(subset(u32, u8, byte_addr, dma.*[3].dad, value)),
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0xDC, 0xDD => dma.*[3].setDmacntL(subset(u16, u8, byte_addr, dma.*[3].word_count, value)),
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0xDE, 0xDF => dma.*[3].setDmacntH(subset(u16, u8, byte_addr, dma.*[3].cnt.raw, value)),
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else => log.warn("Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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else => @compileError("DMA: Unsupported write width"),
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}
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}
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fn warn(comptime format: []const u8, args: anytype) u0 {
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log.warn(format, args);
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return 0;
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}
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/// Function that creates a DMAController. Determines unique DMA Controller behaiour at compile-time
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fn Controller(comptime id: u2) type {
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return struct {
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const Self = @This();
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const sad_mask: u32 = if (id == 0) 0x07FF_FFFF else 0x0FFF_FFFF;
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const dad_mask: u32 = if (id != 3) 0x07FF_FFFF else 0x0FFF_FFFF;
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const WordCount = if (id == 3) u16 else u14;
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/// Write-only. The first address in a DMA transfer. (DMASAD)
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/// Note: use writeSrc instead of manipulating src_addr directly
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sad: u32 = 0x0000_0000,
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/// Write-only. The final address in a DMA transffer. (DMADAD)
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/// Note: Use writeDst instead of manipulatig dst_addr directly
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dad: u32 = 0x0000_0000,
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/// Write-only. The Word Count for the DMA Transfer (DMACNT_L)
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word_count: WordCount = 0,
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/// Read / Write. DMACNT_H
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/// Note: Use writeControl instead of manipulating cnt directly.
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cnt: DmaCnt = .{ .raw = 0x0000 },
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/// Internal. The last successfully read value
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data_latch: u32 = 0x0000_0000,
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/// Internal. Currrent Source Address
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sad_latch: u32 = 0x0000_0000,
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/// Internal. Current Destination Address
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dad_latch: u32 = 0x0000_0000,
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/// Internal. Word Count
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_word_count: WordCount = 0,
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/// Some DMA Transfers are enabled during Hblank / VBlank and / or
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/// have delays. Thefore bit 15 of DMACNT isn't actually something
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/// we can use to control when we do or do not execute a step in a DMA Transfer
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in_progress: bool = false,
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pub fn reset(self: *Self) void {
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self.* = Self.init();
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}
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pub fn setDmasad(self: *Self, addr: u32) void {
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self.sad = addr & sad_mask;
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}
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pub fn setDmadad(self: *Self, addr: u32) void {
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self.dad = addr & dad_mask;
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}
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pub fn setDmacntL(self: *Self, halfword: u16) void {
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self.word_count = @truncate(halfword);
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}
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pub fn dmacntH(self: *const Self) u16 {
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return self.cnt.raw & if (id == 3) 0xFFE0 else 0xF7E0;
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}
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pub fn setDmacntH(self: *Self, halfword: u16) void {
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const new = DmaCnt{ .raw = halfword };
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if (!self.cnt.enabled.read() and new.enabled.read()) {
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// Reload Internals on Rising Edge.
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self.sad_latch = self.sad;
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self.dad_latch = self.dad;
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self._word_count = if (self.word_count == 0) std.math.maxInt(WordCount) else self.word_count;
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// Only a Start Timing of 00 has a DMA Transfer immediately begin
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self.in_progress = new.start_timing.read() == 0b00;
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}
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self.cnt.raw = halfword;
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}
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pub fn setDmacnt(self: *Self, word: u32) void {
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self.setDmacntL(@truncate(word));
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self.setDmacntH(@truncate(word >> 16));
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}
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pub fn step(self: *Self, cpu: *System.Arm7tdmi) void {
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const bus_ptr: *System.Bus7 = @ptrCast(@alignCast(cpu.bus.ptr));
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const is_fifo = (id == 1 or id == 2) and self.cnt.start_timing.read() == 0b11;
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const sad_adj: Adjustment = @enumFromInt(self.cnt.sad_adj.read());
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const dad_adj: Adjustment = if (is_fifo) .Fixed else @enumFromInt(self.cnt.dad_adj.read());
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const transfer_type = is_fifo or self.cnt.transfer_type.read();
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const offset: u32 = if (transfer_type) @sizeOf(u32) else @sizeOf(u16);
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const mask = if (transfer_type) ~@as(u32, 3) else ~@as(u32, 1);
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const sad_addr = self.sad_latch & mask;
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const dad_addr = self.dad_latch & mask;
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if (transfer_type) {
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if (sad_addr >= 0x0200_0000) self.data_latch = cpu.bus.read(u32, sad_addr);
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cpu.bus.write(u32, dad_addr, self.data_latch);
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} else {
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if (sad_addr >= 0x0200_0000) {
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const value: u32 = cpu.bus.read(u16, sad_addr);
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self.data_latch = value << 16 | value;
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}
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cpu.bus.write(u16, dad_addr, @as(u16, @truncate(rotr(u32, self.data_latch, 8 * (dad_addr & 3)))));
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}
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switch (@as(u8, @truncate(sad_addr >> 24))) {
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// according to fleroviux, DMAs with a source address in ROM misbehave
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// the resultant behaviour is that the source address will increment despite what DMAXCNT says
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0x08...0x0D => self.sad_latch +%= offset, // obscure behaviour
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else => switch (sad_adj) {
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.Increment => self.sad_latch +%= offset,
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.Decrement => self.sad_latch -%= offset,
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.IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
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.Fixed => {},
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},
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}
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switch (dad_adj) {
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.Increment, .IncrementReload => self.dad_latch +%= offset,
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.Decrement => self.dad_latch -%= offset,
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.Fixed => {},
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}
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self._word_count -= 1;
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if (self._word_count == 0) {
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if (self.cnt.irq.read()) {
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switch (id) {
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0 => bus_ptr.io.irq.dma0.set(),
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1 => bus_ptr.io.irq.dma1.set(),
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2 => bus_ptr.io.irq.dma2.set(),
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3 => bus_ptr.io.irq.dma3.set(),
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}
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handleInterrupt(.nds7, cpu);
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}
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// If we're not repeating, Fire the IRQs and disable the DMA
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if (!self.cnt.repeat.read()) self.cnt.enabled.unset();
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// We want to disable our internal enabled flag regardless of repeat
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// because we only want to step A DMA that repeats during it's specific
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// timing window
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self.in_progress = false;
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}
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}
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fn poll(self: *Self, comptime kind: Kind) void {
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if (self.in_progress) return; // If there's an ongoing DMA Transfer, exit early
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// No ongoing DMA Transfer, We want to check if we should repeat an existing one
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// Determined by the repeat bit and whether the DMA is in the right start_timing
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switch (kind) {
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.vblank => self.in_progress = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b01,
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.cartridge_slot, .immediate, .special => {},
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}
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// If we determined that the repeat bit is set (and now the Hblank / Vblank DMA is now in progress)
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// Reload internal word count latch
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// Reload internal DAD latch if we are in IncrementRelaod
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if (self.in_progress) {
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self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
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if (@as(Adjustment, @enumFromInt(self.cnt.dad_adj.read())) == .IncrementReload) self.dad_latch = self.dad;
|
||||
}
|
||||
}
|
||||
|
||||
pub fn requestAudio(self: *Self, _: u32) void {
|
||||
comptime std.debug.assert(id == 1 or id == 2);
|
||||
if (self.in_progress) return; // APU must wait their turn
|
||||
|
||||
// DMA May not be configured for handling DMAs
|
||||
if (self.cnt.start_timing.read() != 0b11) return;
|
||||
|
||||
// We Assume the Repeat Bit is Set
|
||||
// We Assume that DAD is set to 0x0400_00A0 or 0x0400_00A4 (fifo_addr)
|
||||
// We Assume DMACNT_L is set to 4
|
||||
|
||||
// FIXME: Safe to just assume whatever DAD is set to is the FIFO Address?
|
||||
// self.dad_latch = fifo_addr;
|
||||
self.cnt.repeat.set();
|
||||
self._word_count = 4;
|
||||
self.in_progress = true;
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
pub fn onVblank(bus: *System.Bus7) void {
|
||||
inline for (0..4) |i| bus.dma[i].poll(.vblank);
|
||||
}
|
||||
|
||||
pub fn step(cpu: *System.Arm7tdmi) bool {
|
||||
const bus: *System.Bus7 = @ptrCast(@alignCast(cpu.bus.ptr));
|
||||
|
||||
inline for (0..4) |i| {
|
||||
if (bus.dma[i].in_progress) {
|
||||
bus.dma[i].step(cpu);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
const Adjustment = enum(u2) {
|
||||
Increment = 0,
|
||||
Decrement = 1,
|
||||
Fixed = 2,
|
||||
IncrementReload = 3,
|
||||
};
|
||||
|
||||
const Kind = enum(u2) {
|
||||
immediate = 0,
|
||||
vblank,
|
||||
cartridge_slot,
|
||||
special,
|
||||
};
|
||||
|
|
@ -12,6 +12,8 @@ const masks = @import("../io.zig").masks;
|
|||
const IntEnable = @import("../io.zig").IntEnable;
|
||||
const IntRequest = @import("../io.zig").IntEnable;
|
||||
|
||||
const dma = @import("dma.zig");
|
||||
|
||||
const log = std.log.scoped(.nds7_io);
|
||||
|
||||
pub const Io = struct {
|
||||
|
|
@ -52,7 +54,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
|
|||
return switch (T) {
|
||||
u32 => switch (address) {
|
||||
// DMA Transfers
|
||||
0x0400_00B0...0x0400_00DC => warn("TODO: impl DMA", .{}),
|
||||
0x0400_00B0...0x0400_00DC => dma.read(T, &bus.dma, address) orelse 0x000_0000,
|
||||
|
||||
// Timers
|
||||
0x0400_0100...0x0400_010C => warn("TODO: impl timer", .{}),
|
||||
|
|
@ -68,7 +70,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
|
|||
u16 => switch (address) {
|
||||
0x0400_0004 => bus.io.ppu.?.nds7.dispstat.raw,
|
||||
// DMA Transfers
|
||||
0x0400_00B0...0x0400_00DE => warn("TODO: impl DMA", .{}),
|
||||
0x0400_00B0...0x0400_00DE => dma.read(T, &bus.dma, address) orelse 0x0000,
|
||||
|
||||
// Timers
|
||||
0x0400_0100...0x0400_010E => warn("TODO: impl timer", .{}),
|
||||
|
|
@ -80,7 +82,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
|
|||
},
|
||||
u8 => switch (address) {
|
||||
// DMA Transfers
|
||||
0x0400_00B0...0x0400_00DF => warn("TODO: impl DMA", .{}),
|
||||
0x0400_00B0...0x0400_00DF => dma.read(T, &bus.dma, address) orelse 0x00,
|
||||
|
||||
// Timers
|
||||
0x0400_0100...0x0400_010F => warn("TODO: impl timer", .{}),
|
||||
|
|
@ -99,7 +101,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
|
|||
switch (T) {
|
||||
u32 => switch (address) {
|
||||
// DMA Transfers
|
||||
0x0400_00B0...0x0400_00DC => log.warn("TODO: impl DMA", .{}),
|
||||
0x0400_00B0...0x0400_00DC => dma.write(T, &bus.dma, address, value),
|
||||
|
||||
// Timers
|
||||
0x0400_0100...0x0400_010C => log.warn("TODO: impl timer", .{}),
|
||||
|
|
@ -114,7 +116,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
|
|||
},
|
||||
u16 => switch (address) {
|
||||
// DMA Transfers
|
||||
0x0400_00B0...0x0400_00DE => log.warn("TODO: impl DMA", .{}),
|
||||
0x0400_00B0...0x0400_00DE => dma.write(T, &bus.dma, address, value),
|
||||
|
||||
// Timers
|
||||
0x0400_0100...0x0400_010E => log.warn("TODO: impl timer", .{}),
|
||||
|
|
@ -127,7 +129,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
|
|||
},
|
||||
u8 => switch (address) {
|
||||
// DMA Transfers
|
||||
0x0400_00B0...0x0400_00DF => log.warn("TODO: impl DMA", .{}),
|
||||
0x0400_00B0...0x0400_00DF => dma.write(T, &bus.dma, address, value),
|
||||
|
||||
// Timers
|
||||
0x0400_0100...0x0400_010F => log.warn("TODO: impl timer", .{}),
|
||||
|
|
@ -167,3 +169,14 @@ const Haltcnt = enum(u2) {
|
|||
};
|
||||
|
||||
const PostFlag = enum(u8) { in_progress = 0, completed };
|
||||
|
||||
pub const DmaCnt = extern union {
|
||||
dad_adj: Bitfield(u16, 5, 2),
|
||||
sad_adj: Bitfield(u16, 7, 2),
|
||||
repeat: Bit(u16, 9),
|
||||
transfer_type: Bit(u16, 10),
|
||||
start_timing: Bitfield(u16, 12, 2),
|
||||
irq: Bit(u16, 14),
|
||||
enabled: Bit(u16, 15),
|
||||
raw: u16,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,6 +8,8 @@ const Vram = @import("ppu/Vram.zig");
|
|||
const EngineA = @import("ppu/engine.zig").EngineA;
|
||||
const EngineB = @import("ppu/engine.zig").EngineB;
|
||||
|
||||
const dma7 = @import("nds7/dma.zig");
|
||||
|
||||
const handleInterrupt = @import("emu.zig").handleInterrupt;
|
||||
|
||||
pub const screen_width = 256;
|
||||
|
|
@ -161,7 +163,9 @@ pub const Ppu = struct {
|
|||
self.io.nds7.dispstat.vblank.set();
|
||||
|
||||
// TODO: Affine BG Latches
|
||||
// TODO: VBlank DMA Transfers
|
||||
|
||||
dma7.onVblank(system.bus7);
|
||||
// TODO: VBlank DMA9 Transfers
|
||||
}
|
||||
|
||||
if (scanline == 262) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue