feat: initial commit

some basic ROMs already boot (ARM946E-S only), working on Armwrestler
and Rockwrestler next so I can ensure CPU compatability for but ARMv5TE
and ARMv4T

src/core/nds7/Scheduler.zig

@@ -0,0 +1,59 @@
+const std = @import("std");
+
+const Bus = @import("Bus.zig");
+
+const PriorityQueue = std.PriorityQueue(Event, void, Event.lessThan);
+const Allocator = std.mem.Allocator;
+
+tick: u64 = 0,
+queue: PriorityQueue,
+
+pub fn init(allocator: Allocator) !@This() {
+    var queue = PriorityQueue.init(allocator, {});
+    try queue.add(.{ .tick = std.math.maxInt(u64), .kind = .heat_death });
+
+    return .{ .queue = queue };
+}
+
+pub fn push(self: *@This(), kind: Event.Kind, offset: u64) void {
+    self.queue.add(.{ .kind = kind, .tick = self.tick + offset }) catch unreachable;
+}
+
+pub fn deinit(self: @This()) void {
+    self.queue.deinit();
+}
+
+pub fn now(self: @This()) u64 {
+    return self.tick;
+}
+
+pub fn next(self: @This()) u64 {
+    @setRuntimeSafety(false);
+    return self.queue.items[0].tick;
+}
+
+pub fn reset(self: *@This()) void {
+    self.tick = 0;
+}
+
+pub fn handle(self: *@This(), bus: *Bus) void {
+    _ = bus;
+    const event = self.queue.remove();
+    const late = self.tick - event.tick;
+    _ = late;
+
+    switch (event.kind) {
+        .heat_death => unreachable,
+    }
+}
+
+pub const Event = struct {
+    tick: u64,
+    kind: Kind,
+
+    pub const Kind = enum { heat_death };
+
+    fn lessThan(_: void, left: @This(), right: @This()) std.math.Order {
+        return std.math.order(left.tick, right.tick);
+    }
+};