chore: rename some io decls
This commit is contained in:
parent
ea3b6ba8fd
commit
c72e36ef6b
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@ -1,7 +1,6 @@
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const std = @import("std");
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const Header = @import("cartridge.zig").Header;
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const SharedIo = @import("io.zig").Io;
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const Scheduler = @import("Scheduler.zig");
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const Allocator = std.mem.Allocator;
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@ -90,13 +89,14 @@ pub fn runFrame(scheduler: *Scheduler, system: System) void {
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}
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// FIXME: Perf win to allocating on the stack instead?
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pub const SharedContext = struct {
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pub const SharedCtx = struct {
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const MiB = 0x100000;
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const KiB = 0x400;
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pub const Io = @import("io.zig").Io;
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const Vram = @import("ppu.zig").Vram;
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io: *SharedIo,
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io: *Io,
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main: *[4 * MiB]u8,
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wram: *Wram,
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vram: *Vram,
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@ -112,7 +112,7 @@ pub const SharedContext = struct {
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const ctx = .{
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.io = blk: {
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const io = try allocator.create(SharedIo);
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const io = try allocator.create(Io);
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io.* = .{};
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break :blk io;
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@ -2,8 +2,7 @@ const std = @import("std");
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const io = @import("io.zig");
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const Scheduler = @import("../Scheduler.zig");
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const SharedIo = @import("../io.zig").Io;
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const SharedContext = @import("../emu.zig").SharedContext;
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const SharedCtx = @import("../emu.zig").SharedCtx;
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const Wram = @import("../emu.zig").Wram;
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const Vram = @import("../ppu.zig").Vram;
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const forceAlign = @import("../emu.zig").forceAlign;
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@ -18,23 +17,23 @@ const log = std.log.scoped(.nds7_bus);
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scheduler: *Scheduler,
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main: *[4 * MiB]u8,
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wram_shr: *Wram,
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shr_wram: *Wram,
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wram: *[64 * KiB]u8,
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vram: *Vram,
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io: io.Io,
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pub fn init(allocator: Allocator, scheduler: *Scheduler, shared_ctx: SharedContext) !@This() {
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pub fn init(allocator: Allocator, scheduler: *Scheduler, ctx: SharedCtx) !@This() {
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const wram = try allocator.create([64 * KiB]u8);
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errdefer allocator.destroy(wram);
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@memset(wram, 0);
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return .{
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.main = shared_ctx.main,
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.wram_shr = shared_ctx.wram,
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.vram = shared_ctx.vram,
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.main = ctx.main,
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.shr_wram = ctx.wram,
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.vram = ctx.vram,
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.wram = wram,
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.scheduler = scheduler,
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.io = io.Io.init(shared_ctx.io),
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.io = io.Io.init(ctx.io),
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};
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}
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@ -66,9 +65,9 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
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return switch (aligned_addr) {
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0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
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0x0300_0000...0x037F_FFFF => switch (self.io.shared.wramcnt.mode.read()) {
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0x0300_0000...0x037F_FFFF => switch (self.io.shr.wramcnt.mode.read()) {
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0b00 => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
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else => self.wram_shr.read(T, .nds7, aligned_addr),
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else => self.shr_wram.read(T, .nds7, aligned_addr),
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},
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0x0380_0000...0x0380_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
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0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
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@ -99,9 +98,9 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
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switch (aligned_addr) {
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0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
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0x0300_0000...0x037F_FFFF => switch (self.io.shared.wramcnt.mode.read()) {
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0x0300_0000...0x037F_FFFF => switch (self.io.shr.wramcnt.mode.read()) {
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0b00 => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
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else => self.wram_shr.write(T, .nds7, aligned_addr, value),
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else => self.shr_wram.write(T, .nds7, aligned_addr, value),
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},
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0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
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0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
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@ -4,37 +4,37 @@ const Bitfield = @import("bitfield").Bitfield;
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const Bit = @import("bitfield").Bit;
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const Bus = @import("Bus.zig");
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const SharedIo = @import("../io.zig").Io;
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const SharedCtx = @import("../emu.zig").SharedCtx;
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const masks = @import("../io.zig").masks;
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const log = std.log.scoped(.nds7_io);
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pub const Io = struct {
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shared: *SharedIo,
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shr: *SharedCtx.Io,
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pub fn init(io: *SharedIo) @This() {
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return .{ .shared = io };
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pub fn init(io: *SharedCtx.Io) @This() {
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return .{ .shr = io };
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}
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};
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pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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return switch (T) {
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u32 => switch (address) {
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0x0400_0208 => @intFromBool(bus.io.shared.ime),
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0x0400_0210 => bus.io.shared.ie,
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0x0400_0214 => bus.io.shared.irq,
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0x0400_0208 => @intFromBool(bus.io.shr.ime),
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0x0400_0210 => bus.io.shr.ie,
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0x0400_0214 => bus.io.shr.irq,
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0x0410_0000 => bus.io.shared.ipc_fifo.recv(.nds7),
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0x0410_0000 => bus.io.shr.ipc_fifo.recv(.nds7),
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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},
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u16 => switch (address) {
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0x0400_0180 => @truncate(bus.io.shared.ipc_fifo._nds7.sync.raw),
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0x0400_0184 => @truncate(bus.io.shared.ipc_fifo._nds7.cnt.raw),
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0x0400_0180 => @truncate(bus.io.shr.ipc_fifo._nds7.sync.raw),
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0x0400_0184 => @truncate(bus.io.shr.ipc_fifo._nds7.cnt.raw),
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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},
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u8 => switch (address) {
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0x0400_0240 => bus.vram.stat().raw,
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0x0400_0241 => bus.io.shared.wramcnt.raw,
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0x0400_0241 => bus.io.shr.wramcnt.raw,
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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},
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else => @compileError(T ++ " is an unsupported bus read type"),
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@ -44,16 +44,16 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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switch (T) {
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u32 => switch (address) {
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0x0400_0208 => bus.io.shared.ime = value & 1 == 1,
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0x0400_0210 => bus.io.shared.ie = value,
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0x0400_0214 => bus.io.shared.irq = value,
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0x0400_0208 => bus.io.shr.ime = value & 1 == 1,
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0x0400_0210 => bus.io.shr.ie = value,
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0x0400_0214 => bus.io.shr.irq = value,
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0x0400_0188 => bus.io.shared.ipc_fifo.send(.nds7, value) catch |e| std.debug.panic("FIFO error: {}", .{e}),
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0x0400_0188 => bus.io.shr.ipc_fifo.send(.nds7, value) catch |e| std.debug.panic("FIFO error: {}", .{e}),
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else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
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},
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u16 => switch (address) {
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0x0400_0180 => bus.io.shared.ipc_fifo.setIpcSync(.nds7, value),
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0x0400_0184 => bus.io.shared.ipc_fifo.setIpcFifoCnt(.nds7, value),
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0x0400_0180 => bus.io.shr.ipc_fifo.setIpcSync(.nds7, value),
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0x0400_0184 => bus.io.shr.ipc_fifo.setIpcFifoCnt(.nds7, value),
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else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
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},
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u8 => switch (address) {
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@ -3,7 +3,7 @@ const io = @import("io.zig");
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const Ppu = @import("../ppu.zig").Ppu;
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const Scheduler = @import("../Scheduler.zig");
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const SharedContext = @import("../emu.zig").SharedContext;
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const SharedCtx = @import("../emu.zig").SharedCtx;
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const Wram = @import("../emu.zig").Wram;
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const forceAlign = @import("../emu.zig").forceAlign;
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@ -22,16 +22,16 @@ ppu: Ppu,
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scheduler: *Scheduler,
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pub fn init(allocator: Allocator, scheduler: *Scheduler, shared_ctx: SharedContext) !@This() {
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pub fn init(allocator: Allocator, scheduler: *Scheduler, ctx: SharedCtx) !@This() {
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const dots_per_cycle = 3; // ARM946E-S runs twice as fast as the ARM7TDMI
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scheduler.push(.{ .nds9 = .draw }, 256 * dots_per_cycle);
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return .{
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.main = shared_ctx.main,
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.wram = shared_ctx.wram,
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.ppu = try Ppu.init(allocator, shared_ctx.vram),
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.main = ctx.main,
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.wram = ctx.wram,
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.ppu = try Ppu.init(allocator, ctx.vram),
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.scheduler = scheduler,
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.io = io.Io.init(shared_ctx.io),
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.io = io.Io.init(ctx.io),
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};
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}
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@ -4,7 +4,7 @@ const Bitfield = @import("bitfield").Bitfield;
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const Bit = @import("bitfield").Bit;
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const Bus = @import("Bus.zig");
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const SharedIo = @import("../io.zig").Io;
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const SharedCtx = @import("../emu.zig").SharedCtx;
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const masks = @import("../io.zig").masks;
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const sext = @import("../../util.zig").sext;
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@ -12,7 +12,7 @@ const sext = @import("../../util.zig").sext;
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const log = std.log.scoped(.nds9_io);
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pub const Io = struct {
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shared: *SharedIo,
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shr: *SharedCtx.Io,
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/// POWCNT1 - Graphics Power Control
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/// Read / Write
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@ -25,17 +25,17 @@ pub const Io = struct {
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div: Divisor = .{},
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sqrt: SquareRootUnit = .{},
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pub fn init(io: *SharedIo) @This() {
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return .{ .shared = io };
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pub fn init(io: *SharedCtx.Io) @This() {
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return .{ .shr = io };
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}
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};
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pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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return switch (T) {
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u32 => switch (address) {
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0x0400_0208 => @intFromBool(bus.io.shared.ime),
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0x0400_0210 => bus.io.shared.ie,
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0x0400_0214 => bus.io.shared.irq,
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0x0400_0208 => @intFromBool(bus.io.shr.ime),
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0x0400_0210 => bus.io.shr.ie,
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0x0400_0214 => bus.io.shr.irq,
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0x0400_02A0 => @truncate(bus.io.div.result),
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0x0400_02A4 => @truncate(bus.io.div.result >> 32),
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@ -43,15 +43,15 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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0x0400_02AC => @truncate(bus.io.div.remainder >> 32),
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0x0400_02B4 => @truncate(bus.io.sqrt.result),
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0x0410_0000 => bus.io.shared.ipc_fifo.recv(.nds9),
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0x0410_0000 => bus.io.shr.ipc_fifo.recv(.nds9),
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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},
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u16 => switch (address) {
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0x0400_0004 => bus.ppu.io.dispstat.raw,
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0x0400_0130 => bus.io.keyinput.load(.Monotonic),
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0x0400_0180 => @truncate(bus.io.shared.ipc_fifo._nds9.sync.raw),
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0x0400_0184 => @truncate(bus.io.shared.ipc_fifo._nds9.cnt.raw),
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0x0400_0180 => @truncate(bus.io.shr.ipc_fifo._nds9.sync.raw),
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0x0400_0184 => @truncate(bus.io.shr.ipc_fifo._nds9.cnt.raw),
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0x0400_0280 => @truncate(bus.io.div.cnt.raw),
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0x0400_02B0 => @truncate(bus.io.sqrt.cnt.raw),
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@ -69,9 +69,9 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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switch (T) {
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u32 => switch (address) {
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0x0400_0000 => bus.ppu.io.dispcnt_a.raw = value,
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0x0400_0180 => bus.io.shared.ipc_fifo.setIpcSync(.nds9, value),
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0x0400_0184 => bus.io.shared.ipc_fifo.setIpcFifoCnt(.nds9, value),
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0x0400_0188 => bus.io.shared.ipc_fifo.send(.nds9, value) catch |e| std.debug.panic("IPC FIFO Error: {}", .{e}),
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0x0400_0180 => bus.io.shr.ipc_fifo.setIpcSync(.nds9, value),
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0x0400_0184 => bus.io.shr.ipc_fifo.setIpcFifoCnt(.nds9, value),
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0x0400_0188 => bus.io.shr.ipc_fifo.send(.nds9, value) catch |e| std.debug.panic("IPC FIFO Error: {}", .{e}),
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0x0400_0240 => {
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bus.ppu.vram.io.cnt_a.raw = @truncate(value >> 0); // 0x0400_0240
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@ -80,9 +80,9 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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bus.ppu.vram.io.cnt_d.raw = @truncate(value >> 24); // 0x0400_0243
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},
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0x0400_0208 => bus.io.shared.ime = value & 1 == 1,
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0x0400_0210 => bus.io.shared.ie = value,
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0x0400_0214 => bus.io.shared.irq = value,
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0x0400_0208 => bus.io.shr.ime = value & 1 == 1,
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0x0400_0210 => bus.io.shr.ie = value,
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0x0400_0214 => bus.io.shr.irq = value,
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0x0400_0290 => {
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bus.io.div.numerator = masks.mask(bus.io.div.numerator, value, 0xFFFF_FFFF);
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@ -114,9 +114,9 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
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},
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u16 => switch (address) {
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0x0400_0180 => bus.io.shared.ipc_fifo.setIpcSync(.nds9, value),
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0x0400_0184 => bus.io.shared.ipc_fifo.setIpcFifoCnt(.nds9, value),
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0x0400_0208 => bus.io.shared.ime = value & 1 == 1,
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0x0400_0180 => bus.io.shr.ipc_fifo.setIpcSync(.nds9, value),
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0x0400_0184 => bus.io.shr.ipc_fifo.setIpcFifoCnt(.nds9, value),
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0x0400_0208 => bus.io.shr.ime = value & 1 == 1,
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0x0400_0280 => {
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bus.io.div.cnt.raw = value;
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@ -160,8 +160,8 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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bus.ppu.vram.update();
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},
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0x0400_0247 => {
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bus.io.shared.wramcnt.raw = value;
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bus.wram.update(bus.io.shared.wramcnt);
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bus.io.shr.wramcnt.raw = value;
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bus.wram.update(bus.io.shr.wramcnt);
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},
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0x0400_0248 => {
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bus.ppu.vram.io.cnt_h.raw = value;
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10
src/main.zig
10
src/main.zig
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@ -4,7 +4,7 @@ const clap = @import("zig-clap");
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const emu = @import("core/emu.zig");
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const Ui = @import("platform.zig").Ui;
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const SharedContext = @import("core/emu.zig").SharedContext;
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const SharedCtx = @import("core/emu.zig").SharedCtx;
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const System = @import("core/emu.zig").System;
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const Scheduler = @import("core/Scheduler.zig");
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@ -34,8 +34,8 @@ pub fn main() !void {
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const rom_file = try std.fs.cwd().openFile(rom_path, .{});
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defer rom_file.close();
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const shared_ctx = try SharedContext.init(allocator);
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defer shared_ctx.deinit(allocator);
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const ctx = try SharedCtx.init(allocator);
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defer ctx.deinit(allocator);
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var scheduler = try Scheduler.init(allocator);
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defer scheduler.deinit();
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@ -47,8 +47,8 @@ pub fn main() !void {
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var cp15 = System.Cp15{};
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var bus7 = try System.Bus7.init(allocator, &scheduler, shared_ctx);
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var bus9 = try System.Bus9.init(allocator, &scheduler, shared_ctx);
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var bus7 = try System.Bus7.init(allocator, &scheduler, ctx);
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var bus9 = try System.Bus9.init(allocator, &scheduler, ctx);
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var arm7tdmi = System.Arm7tdmi.init(IScheduler.init(&scheduler), IBus.init(&bus7));
|
||||
var arm946es = System.Arm946es.init(IScheduler.init(&scheduler), IBus.init(&bus9), ICoprocessor.init(&cp15));
|
||||
|
|
Loading…
Reference in New Issue