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chore: rename some io decls

This commit is contained in:
Rekai Nyangadzayi Musuka 2023-10-08 16:38:53 -05:00
parent ea3b6ba8fd
commit c72e36ef6b
6 changed files with 64 additions and 65 deletions
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8
src/core/emu.zig
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@ -1,7 +1,6 @@
const std = @import("std"); const std = @import("std");
const Header = @import("cartridge.zig").Header; const Header = @import("cartridge.zig").Header;
const SharedIo = @import("io.zig").Io;
const Scheduler = @import("Scheduler.zig"); const Scheduler = @import("Scheduler.zig");
const Allocator = std.mem.Allocator; const Allocator = std.mem.Allocator;
@ -90,13 +89,14 @@ pub fn runFrame(scheduler: *Scheduler, system: System) void {
} }
// FIXME: Perf win to allocating on the stack instead? // FIXME: Perf win to allocating on the stack instead?
pub const SharedContext = struct { pub const SharedCtx = struct {
const MiB = 0x100000; const MiB = 0x100000;
const KiB = 0x400; const KiB = 0x400;
pub const Io = @import("io.zig").Io;
const Vram = @import("ppu.zig").Vram; const Vram = @import("ppu.zig").Vram;
io: *SharedIo, io: *Io,
main: *[4 * MiB]u8, main: *[4 * MiB]u8,
wram: *Wram, wram: *Wram,
vram: *Vram, vram: *Vram,
@ -112,7 +112,7 @@ pub const SharedContext = struct {
const ctx = .{ const ctx = .{
.io = blk: { .io = blk: {
const io = try allocator.create(SharedIo); const io = try allocator.create(Io);
io.* = .{}; io.* = .{};
break :blk io; break :blk io;

23
src/core/nds7/Bus.zig
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@ -2,8 +2,7 @@ const std = @import("std");
const io = @import("io.zig"); const io = @import("io.zig");
const Scheduler = @import("../Scheduler.zig"); const Scheduler = @import("../Scheduler.zig");
const SharedIo = @import("../io.zig").Io; const SharedCtx = @import("../emu.zig").SharedCtx;
const SharedContext = @import("../emu.zig").SharedContext;
const Wram = @import("../emu.zig").Wram; const Wram = @import("../emu.zig").Wram;
const Vram = @import("../ppu.zig").Vram; const Vram = @import("../ppu.zig").Vram;
const forceAlign = @import("../emu.zig").forceAlign; const forceAlign = @import("../emu.zig").forceAlign;
@ -18,23 +17,23 @@ const log = std.log.scoped(.nds7_bus);
scheduler: *Scheduler, scheduler: *Scheduler,
main: *[4 * MiB]u8, main: *[4 * MiB]u8,
wram_shr: *Wram, shr_wram: *Wram,
wram: *[64 * KiB]u8, wram: *[64 * KiB]u8,
vram: *Vram, vram: *Vram,
io: io.Io, io: io.Io,
pub fn init(allocator: Allocator, scheduler: *Scheduler, shared_ctx: SharedContext) !@This() { pub fn init(allocator: Allocator, scheduler: *Scheduler, ctx: SharedCtx) !@This() {
const wram = try allocator.create([64 * KiB]u8); const wram = try allocator.create([64 * KiB]u8);
errdefer allocator.destroy(wram); errdefer allocator.destroy(wram);
@memset(wram, 0); @memset(wram, 0);
return .{ return .{
.main = shared_ctx.main, .main = ctx.main,
.wram_shr = shared_ctx.wram, .shr_wram = ctx.wram,
.vram = shared_ctx.vram, .vram = ctx.vram,
.wram = wram, .wram = wram,
.scheduler = scheduler, .scheduler = scheduler,
.io = io.Io.init(shared_ctx.io), .io = io.Io.init(ctx.io),
}; };
} }
@ -66,9 +65,9 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
return switch (aligned_addr) { return switch (aligned_addr) {
0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]), 0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
0x0300_0000...0x037F_FFFF => switch (self.io.shared.wramcnt.mode.read()) { 0x0300_0000...0x037F_FFFF => switch (self.io.shr.wramcnt.mode.read()) {
0b00 => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]), 0b00 => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
else => self.wram_shr.read(T, .nds7, aligned_addr), else => self.shr_wram.read(T, .nds7, aligned_addr),
}, },
0x0380_0000...0x0380_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]), 0x0380_0000...0x0380_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr), 0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
@ -99,9 +98,9 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
switch (aligned_addr) { switch (aligned_addr) {
0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value), 0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
0x0300_0000...0x037F_FFFF => switch (self.io.shared.wramcnt.mode.read()) { 0x0300_0000...0x037F_FFFF => switch (self.io.shr.wramcnt.mode.read()) {
0b00 => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value), 0b00 => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
else => self.wram_shr.write(T, .nds7, aligned_addr, value), else => self.shr_wram.write(T, .nds7, aligned_addr, value),
}, },
0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value), 0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value), 0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),

34
src/core/nds7/io.zig
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@ -4,37 +4,37 @@ const Bitfield = @import("bitfield").Bitfield;
const Bit = @import("bitfield").Bit; const Bit = @import("bitfield").Bit;
const Bus = @import("Bus.zig"); const Bus = @import("Bus.zig");
const SharedIo = @import("../io.zig").Io; const SharedCtx = @import("../emu.zig").SharedCtx;
const masks = @import("../io.zig").masks; const masks = @import("../io.zig").masks;
const log = std.log.scoped(.nds7_io); const log = std.log.scoped(.nds7_io);
pub const Io = struct { pub const Io = struct {
shared: *SharedIo, shr: *SharedCtx.Io,
pub fn init(io: *SharedIo) @This() { pub fn init(io: *SharedCtx.Io) @This() {
return .{ .shared = io }; return .{ .shr = io };
} }
}; };
pub fn read(bus: *const Bus, comptime T: type, address: u32) T { pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
return switch (T) { return switch (T) {
u32 => switch (address) { u32 => switch (address) {
0x0400_0208 => @intFromBool(bus.io.shared.ime), 0x0400_0208 => @intFromBool(bus.io.shr.ime),
0x0400_0210 => bus.io.shared.ie, 0x0400_0210 => bus.io.shr.ie,
0x0400_0214 => bus.io.shared.irq, 0x0400_0214 => bus.io.shr.irq,
0x0410_0000 => bus.io.shared.ipc_fifo.recv(.nds7), 0x0410_0000 => bus.io.shr.ipc_fifo.recv(.nds7),
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }), else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
}, },
u16 => switch (address) { u16 => switch (address) {
0x0400_0180 => @truncate(bus.io.shared.ipc_fifo._nds7.sync.raw), 0x0400_0180 => @truncate(bus.io.shr.ipc_fifo._nds7.sync.raw),
0x0400_0184 => @truncate(bus.io.shared.ipc_fifo._nds7.cnt.raw), 0x0400_0184 => @truncate(bus.io.shr.ipc_fifo._nds7.cnt.raw),
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }), else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
}, },
u8 => switch (address) { u8 => switch (address) {
0x0400_0240 => bus.vram.stat().raw, 0x0400_0240 => bus.vram.stat().raw,
0x0400_0241 => bus.io.shared.wramcnt.raw, 0x0400_0241 => bus.io.shr.wramcnt.raw,
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }), else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
}, },
else => @compileError(T ++ " is an unsupported bus read type"), else => @compileError(T ++ " is an unsupported bus read type"),
@ -44,16 +44,16 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void { pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
switch (T) { switch (T) {
u32 => switch (address) { u32 => switch (address) {
0x0400_0208 => bus.io.shared.ime = value & 1 == 1, 0x0400_0208 => bus.io.shr.ime = value & 1 == 1,
0x0400_0210 => bus.io.shared.ie = value, 0x0400_0210 => bus.io.shr.ie = value,
0x0400_0214 => bus.io.shared.irq = value, 0x0400_0214 => bus.io.shr.irq = value,
0x0400_0188 => bus.io.shared.ipc_fifo.send(.nds7, value) catch |e| std.debug.panic("FIFO error: {}", .{e}), 0x0400_0188 => bus.io.shr.ipc_fifo.send(.nds7, value) catch |e| std.debug.panic("FIFO error: {}", .{e}),
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }), else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
}, },
u16 => switch (address) { u16 => switch (address) {
0x0400_0180 => bus.io.shared.ipc_fifo.setIpcSync(.nds7, value), 0x0400_0180 => bus.io.shr.ipc_fifo.setIpcSync(.nds7, value),
0x0400_0184 => bus.io.shared.ipc_fifo.setIpcFifoCnt(.nds7, value), 0x0400_0184 => bus.io.shr.ipc_fifo.setIpcFifoCnt(.nds7, value),
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }), else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
}, },
u8 => switch (address) { u8 => switch (address) {

12
src/core/nds9/Bus.zig
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@ -3,7 +3,7 @@ const io = @import("io.zig");
const Ppu = @import("../ppu.zig").Ppu; const Ppu = @import("../ppu.zig").Ppu;
const Scheduler = @import("../Scheduler.zig"); const Scheduler = @import("../Scheduler.zig");
const SharedContext = @import("../emu.zig").SharedContext; const SharedCtx = @import("../emu.zig").SharedCtx;
const Wram = @import("../emu.zig").Wram; const Wram = @import("../emu.zig").Wram;
const forceAlign = @import("../emu.zig").forceAlign; const forceAlign = @import("../emu.zig").forceAlign;
@ -22,16 +22,16 @@ ppu: Ppu,
scheduler: *Scheduler, scheduler: *Scheduler,
pub fn init(allocator: Allocator, scheduler: *Scheduler, shared_ctx: SharedContext) !@This() { pub fn init(allocator: Allocator, scheduler: *Scheduler, ctx: SharedCtx) !@This() {
const dots_per_cycle = 3; // ARM946E-S runs twice as fast as the ARM7TDMI const dots_per_cycle = 3; // ARM946E-S runs twice as fast as the ARM7TDMI
scheduler.push(.{ .nds9 = .draw }, 256 * dots_per_cycle); scheduler.push(.{ .nds9 = .draw }, 256 * dots_per_cycle);
return .{ return .{
.main = shared_ctx.main, .main = ctx.main,
.wram = shared_ctx.wram, .wram = ctx.wram,
.ppu = try Ppu.init(allocator, shared_ctx.vram), .ppu = try Ppu.init(allocator, ctx.vram),
.scheduler = scheduler, .scheduler = scheduler,
.io = io.Io.init(shared_ctx.io), .io = io.Io.init(ctx.io),
}; };
} }

42
src/core/nds9/io.zig
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@ -4,7 +4,7 @@ const Bitfield = @import("bitfield").Bitfield;
const Bit = @import("bitfield").Bit; const Bit = @import("bitfield").Bit;
const Bus = @import("Bus.zig"); const Bus = @import("Bus.zig");
const SharedIo = @import("../io.zig").Io; const SharedCtx = @import("../emu.zig").SharedCtx;
const masks = @import("../io.zig").masks; const masks = @import("../io.zig").masks;
const sext = @import("../../util.zig").sext; const sext = @import("../../util.zig").sext;
@ -12,7 +12,7 @@ const sext = @import("../../util.zig").sext;
const log = std.log.scoped(.nds9_io); const log = std.log.scoped(.nds9_io);
pub const Io = struct { pub const Io = struct {
shared: *SharedIo, shr: *SharedCtx.Io,
/// POWCNT1 - Graphics Power Control /// POWCNT1 - Graphics Power Control
/// Read / Write /// Read / Write
@ -25,17 +25,17 @@ pub const Io = struct {
div: Divisor = .{}, div: Divisor = .{},
sqrt: SquareRootUnit = .{}, sqrt: SquareRootUnit = .{},
pub fn init(io: *SharedIo) @This() { pub fn init(io: *SharedCtx.Io) @This() {
return .{ .shared = io }; return .{ .shr = io };
} }
}; };
pub fn read(bus: *const Bus, comptime T: type, address: u32) T { pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
return switch (T) { return switch (T) {
u32 => switch (address) { u32 => switch (address) {
0x0400_0208 => @intFromBool(bus.io.shared.ime), 0x0400_0208 => @intFromBool(bus.io.shr.ime),
0x0400_0210 => bus.io.shared.ie, 0x0400_0210 => bus.io.shr.ie,
0x0400_0214 => bus.io.shared.irq, 0x0400_0214 => bus.io.shr.irq,
0x0400_02A0 => @truncate(bus.io.div.result), 0x0400_02A0 => @truncate(bus.io.div.result),
0x0400_02A4 => @truncate(bus.io.div.result >> 32), 0x0400_02A4 => @truncate(bus.io.div.result >> 32),
@ -43,15 +43,15 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
0x0400_02AC => @truncate(bus.io.div.remainder >> 32), 0x0400_02AC => @truncate(bus.io.div.remainder >> 32),
0x0400_02B4 => @truncate(bus.io.sqrt.result), 0x0400_02B4 => @truncate(bus.io.sqrt.result),
0x0410_0000 => bus.io.shared.ipc_fifo.recv(.nds9), 0x0410_0000 => bus.io.shr.ipc_fifo.recv(.nds9),
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }), else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
}, },
u16 => switch (address) { u16 => switch (address) {
0x0400_0004 => bus.ppu.io.dispstat.raw, 0x0400_0004 => bus.ppu.io.dispstat.raw,
0x0400_0130 => bus.io.keyinput.load(.Monotonic), 0x0400_0130 => bus.io.keyinput.load(.Monotonic),
0x0400_0180 => @truncate(bus.io.shared.ipc_fifo._nds9.sync.raw), 0x0400_0180 => @truncate(bus.io.shr.ipc_fifo._nds9.sync.raw),
0x0400_0184 => @truncate(bus.io.shared.ipc_fifo._nds9.cnt.raw), 0x0400_0184 => @truncate(bus.io.shr.ipc_fifo._nds9.cnt.raw),
0x0400_0280 => @truncate(bus.io.div.cnt.raw), 0x0400_0280 => @truncate(bus.io.div.cnt.raw),
0x0400_02B0 => @truncate(bus.io.sqrt.cnt.raw), 0x0400_02B0 => @truncate(bus.io.sqrt.cnt.raw),
@ -69,9 +69,9 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
switch (T) { switch (T) {
u32 => switch (address) { u32 => switch (address) {
0x0400_0000 => bus.ppu.io.dispcnt_a.raw = value, 0x0400_0000 => bus.ppu.io.dispcnt_a.raw = value,
0x0400_0180 => bus.io.shared.ipc_fifo.setIpcSync(.nds9, value), 0x0400_0180 => bus.io.shr.ipc_fifo.setIpcSync(.nds9, value),
0x0400_0184 => bus.io.shared.ipc_fifo.setIpcFifoCnt(.nds9, value), 0x0400_0184 => bus.io.shr.ipc_fifo.setIpcFifoCnt(.nds9, value),
0x0400_0188 => bus.io.shared.ipc_fifo.send(.nds9, value) catch |e| std.debug.panic("IPC FIFO Error: {}", .{e}), 0x0400_0188 => bus.io.shr.ipc_fifo.send(.nds9, value) catch |e| std.debug.panic("IPC FIFO Error: {}", .{e}),
0x0400_0240 => { 0x0400_0240 => {
bus.ppu.vram.io.cnt_a.raw = @truncate(value >> 0); // 0x0400_0240 bus.ppu.vram.io.cnt_a.raw = @truncate(value >> 0); // 0x0400_0240
@ -80,9 +80,9 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
bus.ppu.vram.io.cnt_d.raw = @truncate(value >> 24); // 0x0400_0243 bus.ppu.vram.io.cnt_d.raw = @truncate(value >> 24); // 0x0400_0243
}, },
0x0400_0208 => bus.io.shared.ime = value & 1 == 1, 0x0400_0208 => bus.io.shr.ime = value & 1 == 1,
0x0400_0210 => bus.io.shared.ie = value, 0x0400_0210 => bus.io.shr.ie = value,
0x0400_0214 => bus.io.shared.irq = value, 0x0400_0214 => bus.io.shr.irq = value,
0x0400_0290 => { 0x0400_0290 => {
bus.io.div.numerator = masks.mask(bus.io.div.numerator, value, 0xFFFF_FFFF); bus.io.div.numerator = masks.mask(bus.io.div.numerator, value, 0xFFFF_FFFF);
@ -114,9 +114,9 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }), else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
}, },
u16 => switch (address) { u16 => switch (address) {
0x0400_0180 => bus.io.shared.ipc_fifo.setIpcSync(.nds9, value), 0x0400_0180 => bus.io.shr.ipc_fifo.setIpcSync(.nds9, value),
0x0400_0184 => bus.io.shared.ipc_fifo.setIpcFifoCnt(.nds9, value), 0x0400_0184 => bus.io.shr.ipc_fifo.setIpcFifoCnt(.nds9, value),
0x0400_0208 => bus.io.shared.ime = value & 1 == 1, 0x0400_0208 => bus.io.shr.ime = value & 1 == 1,
0x0400_0280 => { 0x0400_0280 => {
bus.io.div.cnt.raw = value; bus.io.div.cnt.raw = value;
@ -160,8 +160,8 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
bus.ppu.vram.update(); bus.ppu.vram.update();
}, },
0x0400_0247 => { 0x0400_0247 => {
bus.io.shared.wramcnt.raw = value; bus.io.shr.wramcnt.raw = value;
bus.wram.update(bus.io.shared.wramcnt); bus.wram.update(bus.io.shr.wramcnt);
}, },
0x0400_0248 => { 0x0400_0248 => {
bus.ppu.vram.io.cnt_h.raw = value; bus.ppu.vram.io.cnt_h.raw = value;

10
src/main.zig
View File

@ -4,7 +4,7 @@ const clap = @import("zig-clap");
const emu = @import("core/emu.zig"); const emu = @import("core/emu.zig");
const Ui = @import("platform.zig").Ui; const Ui = @import("platform.zig").Ui;
const SharedContext = @import("core/emu.zig").SharedContext; const SharedCtx = @import("core/emu.zig").SharedCtx;
const System = @import("core/emu.zig").System; const System = @import("core/emu.zig").System;
const Scheduler = @import("core/Scheduler.zig"); const Scheduler = @import("core/Scheduler.zig");
@ -34,8 +34,8 @@ pub fn main() !void {
const rom_file = try std.fs.cwd().openFile(rom_path, .{}); const rom_file = try std.fs.cwd().openFile(rom_path, .{});
defer rom_file.close(); defer rom_file.close();
const shared_ctx = try SharedContext.init(allocator); const ctx = try SharedCtx.init(allocator);
defer shared_ctx.deinit(allocator); defer ctx.deinit(allocator);
var scheduler = try Scheduler.init(allocator); var scheduler = try Scheduler.init(allocator);
defer scheduler.deinit(); defer scheduler.deinit();
@ -47,8 +47,8 @@ pub fn main() !void {
var cp15 = System.Cp15{}; var cp15 = System.Cp15{};
var bus7 = try System.Bus7.init(allocator, &scheduler, shared_ctx); var bus7 = try System.Bus7.init(allocator, &scheduler, ctx);
var bus9 = try System.Bus9.init(allocator, &scheduler, shared_ctx); var bus9 = try System.Bus9.init(allocator, &scheduler, ctx);
var arm7tdmi = System.Arm7tdmi.init(IScheduler.init(&scheduler), IBus.init(&bus7)); var arm7tdmi = System.Arm7tdmi.init(IScheduler.init(&scheduler), IBus.init(&bus7));
var arm946es = System.Arm946es.init(IScheduler.init(&scheduler), IBus.init(&bus9), ICoprocessor.init(&cp15)); var arm946es = System.Arm946es.init(IScheduler.init(&scheduler), IBus.init(&bus9), ICoprocessor.init(&cp15));