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chore: rename some io decls

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This commit is contained in:
Rekai Nyangadzayi Musuka
2023-10-08 16:38:53 -05:00
parent ea3b6ba8fd
commit c72e36ef6b
6 changed files with 64 additions and 65 deletions
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23
src/core/nds7/Bus.zig
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@@ -2,8 +2,7 @@ const std = @import("std");
const io = @import("io.zig");
const Scheduler = @import("../Scheduler.zig");
const SharedIo = @import("../io.zig").Io;
const SharedContext = @import("../emu.zig").SharedContext;
const SharedCtx = @import("../emu.zig").SharedCtx;
const Wram = @import("../emu.zig").Wram;
const Vram = @import("../ppu.zig").Vram;
const forceAlign = @import("../emu.zig").forceAlign;
@@ -18,23 +17,23 @@ const log = std.log.scoped(.nds7_bus);
scheduler: *Scheduler,
main: *[4 * MiB]u8,
wram_shr: *Wram,
shr_wram: *Wram,
wram: *[64 * KiB]u8,
vram: *Vram,
io: io.Io,
pub fn init(allocator: Allocator, scheduler: *Scheduler, shared_ctx: SharedContext) !@This() {
pub fn init(allocator: Allocator, scheduler: *Scheduler, ctx: SharedCtx) !@This() {
const wram = try allocator.create([64 * KiB]u8);
errdefer allocator.destroy(wram);
@memset(wram, 0);
return .{
.main = shared_ctx.main,
.wram_shr = shared_ctx.wram,
.vram = shared_ctx.vram,
.main = ctx.main,
.shr_wram = ctx.wram,
.vram = ctx.vram,
.wram = wram,
.scheduler = scheduler,
.io = io.Io.init(shared_ctx.io),
.io = io.Io.init(ctx.io),
};
}
@@ -66,9 +65,9 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
return switch (aligned_addr) {
0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
0x0300_0000...0x037F_FFFF => switch (self.io.shared.wramcnt.mode.read()) {
0x0300_0000...0x037F_FFFF => switch (self.io.shr.wramcnt.mode.read()) {
0b00 => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
else => self.wram_shr.read(T, .nds7, aligned_addr),
else => self.shr_wram.read(T, .nds7, aligned_addr),
},
0x0380_0000...0x0380_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
@@ -99,9 +98,9 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
switch (aligned_addr) {
0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
0x0300_0000...0x037F_FFFF => switch (self.io.shared.wramcnt.mode.read()) {
0x0300_0000...0x037F_FFFF => switch (self.io.shr.wramcnt.mode.read()) {
0b00 => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
else => self.wram_shr.write(T, .nds7, aligned_addr, value),
else => self.shr_wram.write(T, .nds7, aligned_addr, value),
},
0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),

34
src/core/nds7/io.zig
View File

@@ -4,37 +4,37 @@ const Bitfield = @import("bitfield").Bitfield;
const Bit = @import("bitfield").Bit;
const Bus = @import("Bus.zig");
const SharedIo = @import("../io.zig").Io;
const SharedCtx = @import("../emu.zig").SharedCtx;
const masks = @import("../io.zig").masks;
const log = std.log.scoped(.nds7_io);
pub const Io = struct {
shared: *SharedIo,
shr: *SharedCtx.Io,
pub fn init(io: *SharedIo) @This() {
return .{ .shared = io };
pub fn init(io: *SharedCtx.Io) @This() {
return .{ .shr = io };
}
};
pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
return switch (T) {
u32 => switch (address) {
0x0400_0208 => @intFromBool(bus.io.shared.ime),
0x0400_0210 => bus.io.shared.ie,
0x0400_0214 => bus.io.shared.irq,
0x0400_0208 => @intFromBool(bus.io.shr.ime),
0x0400_0210 => bus.io.shr.ie,
0x0400_0214 => bus.io.shr.irq,
0x0410_0000 => bus.io.shared.ipc_fifo.recv(.nds7),
0x0410_0000 => bus.io.shr.ipc_fifo.recv(.nds7),
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
},
u16 => switch (address) {
0x0400_0180 => @truncate(bus.io.shared.ipc_fifo._nds7.sync.raw),
0x0400_0184 => @truncate(bus.io.shared.ipc_fifo._nds7.cnt.raw),
0x0400_0180 => @truncate(bus.io.shr.ipc_fifo._nds7.sync.raw),
0x0400_0184 => @truncate(bus.io.shr.ipc_fifo._nds7.cnt.raw),
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
},
u8 => switch (address) {
0x0400_0240 => bus.vram.stat().raw,
0x0400_0241 => bus.io.shared.wramcnt.raw,
0x0400_0241 => bus.io.shr.wramcnt.raw,
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
},
else => @compileError(T ++ " is an unsupported bus read type"),
@@ -44,16 +44,16 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
switch (T) {
u32 => switch (address) {
0x0400_0208 => bus.io.shared.ime = value & 1 == 1,
0x0400_0210 => bus.io.shared.ie = value,
0x0400_0214 => bus.io.shared.irq = value,
0x0400_0208 => bus.io.shr.ime = value & 1 == 1,
0x0400_0210 => bus.io.shr.ie = value,
0x0400_0214 => bus.io.shr.irq = value,
0x0400_0188 => bus.io.shared.ipc_fifo.send(.nds7, value) catch |e| std.debug.panic("FIFO error: {}", .{e}),
0x0400_0188 => bus.io.shr.ipc_fifo.send(.nds7, value) catch |e| std.debug.panic("FIFO error: {}", .{e}),
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
},
u16 => switch (address) {
0x0400_0180 => bus.io.shared.ipc_fifo.setIpcSync(.nds7, value),
0x0400_0184 => bus.io.shared.ipc_fifo.setIpcFifoCnt(.nds7, value),
0x0400_0180 => bus.io.shr.ipc_fifo.setIpcSync(.nds7, value),
0x0400_0184 => bus.io.shr.ipc_fifo.setIpcFifoCnt(.nds7, value),
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
},
u8 => switch (address) {