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chore: stub NDS7 DMA registers

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This commit is contained in:
Rekai Nyangadzayi Musuka
2023-10-09 19:23:36 -05:00
parent 7f4dad485f
commit 95dfeceb00
4 changed files with 115 additions and 31 deletions
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40
src/core/nds7/io.zig
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@@ -45,6 +45,13 @@ pub const Io = struct {
pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
return switch (T) {
u32 => switch (address) {
// DMA Transfers
0x0400_00B0...0x0400_00DC => warn("TODO: Implement DMA", .{}),
// Timers
0x0400_0100...0x0400_010C => warn("TODO: Implement Timer", .{}),
0x0400_0180 => bus.io.shr.ipc._nds7.sync.raw,
0x0400_0208 => @intFromBool(bus.io.ime),
0x0400_0210 => bus.io.ie.raw,
0x0400_0214 => bus.io.irq.raw,
@@ -53,11 +60,23 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
},
u16 => switch (address) {
// DMA Transfers
0x0400_00B0...0x0400_00DE => warn("TODO: Implement DMA", .{}),
// Timers
0x0400_0100...0x0400_010E => warn("TODO: Implement Timer", .{}),
0x0400_0180 => @truncate(bus.io.shr.ipc._nds7.sync.raw),
0x0400_0184 => @truncate(bus.io.shr.ipc._nds7.cnt.raw),
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
},
u8 => switch (address) {
// DMA Transfers
0x0400_00B0...0x0400_00DF => warn("TODO: Implement DMA", .{}),
// Timers
0x0400_0100...0x0400_010F => warn("TODO: Implement Timer", .{}),
0x0400_0240 => bus.vram.stat().raw,
0x0400_0241 => bus.io.shr.wramcnt.raw,
@@ -71,19 +90,38 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
switch (T) {
u32 => switch (address) {
// DMA Transfers
0x0400_00B0...0x0400_00DC => log.warn("TODO: Implement DMA", .{}),
// Timers
0x0400_0100...0x0400_010C => log.warn("TODO: Implement Timer", .{}),
0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds7, value),
0x0400_0208 => bus.io.ime = value & 1 == 1,
0x0400_0210 => bus.io.ie.raw = value,
0x0400_0214 => bus.io.irq.raw &= ~value,
0x0400_0188 => bus.io.shr.ipc.send(.nds7, value) catch |e| std.debug.panic("FIFO error: {}", .{e}),
0x0400_0188 => bus.io.shr.ipc.send(.nds7, value),
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
},
u16 => switch (address) {
// DMA Transfers
0x0400_00B0...0x0400_00DE => log.warn("TODO: Implement DMA", .{}),
// Timers
0x0400_0100...0x0400_010E => log.warn("TODO: Implement Timer", .{}),
0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds7, value),
0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds7, value),
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
},
u8 => switch (address) {
// DMA Transfers
0x0400_00B0...0x0400_00DF => log.warn("TODO: Implement DMA", .{}),
// Timers
0x0400_0100...0x0400_010F => log.warn("TODO: Implement Timer", .{}),
0x0400_0208 => bus.io.ime = value & 1 == 1,
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
},