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chore(cp15): ignore cp15 registers written to by libnds crt0 (?)

This commit is contained in:
Rekai Nyangadzayi Musuka 2023-11-02 00:24:19 -05:00
parent 1a56a1a285
commit 81c17b9965
1 changed files with 56 additions and 17 deletions
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73
src/core/nds9/Cp15.zig
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@ -2,6 +2,8 @@ const std = @import("std");
const log = std.log.scoped(.cp15); const log = std.log.scoped(.cp15);
const panic_on_unimplemented: bool = true;
control: u32 = 0x0005_2078, control: u32 = 0x0005_2078,
dtcm_size_base: u32 = 0x0300_000A, dtcm_size_base: u32 = 0x0300_000A,
itcm_size_base: u32 = 0x0000_0020, itcm_size_base: u32 = 0x0000_0020,
@ -41,22 +43,57 @@ pub fn write(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void
self.control = (value & ~zeroes) | ones; self.control = (value & ~zeroes) | ones;
}, },
0b000_0010_0000_000 => log.err("TODO: write to PU cachability bits (data/unified region)", .{}),
0b000_0010_0000_001 => log.err("TODO: write to PU cachability bits (instruction region)", .{}),
0b000_0011_0000_000 => log.err("TODO: write to PU cache write-bufferability bits (data protection region)", .{}),
0b000_0101_0000_000 => log.err("TODO: write to access permission protection region (data/unified)", .{}),
0b000_0101_0000_001 => log.err("TODO: write to access permission protection region (insruction)", .{}),
0b000_0101_0000_010 => log.err("TODO: write to extended access permission protection region (data/unified)", .{}),
0b000_0101_0000_011 => log.err("TODO: write to extended access permission protection region (insruction)", .{}),
0b000_0110_0000_000,
0b000_0110_0001_000,
0b000_0110_0010_000,
0b000_0110_0011_000,
0b000_0110_0100_000,
0b000_0110_0101_000,
0b000_0110_0110_000,
0b000_0110_0111_000,
=> log.err("TODO: write to PU data/unified region #{}", .{cm}),
0b000_0110_0000_001,
0b000_0110_0001_001,
0b000_0110_0010_001,
0b000_0110_0011_001,
0b000_0110_0100_001,
0b000_0110_0101_001,
0b000_0110_0110_001,
0b000_0110_0111_001,
=> log.err("TODO: write to PU instruction region #{}", .{cm}),
0b000_0111_0000_100 => log.err("TODO: halt ARM946E-S", .{}),
0b000_0111_0101_000 => log.err("TODO: invalidate instruction cache", .{}),
0b000_0111_0110_000 => log.err("TODO: invalidate data cache", .{}),
0b000_0111_1010_100 => log.err("TODO: drain write buffer", .{}),
0b000_1001_0001_000 => { // Data TCM Size / Base 0b000_1001_0001_000 => { // Data TCM Size / Base
const zeroes: u32 = 0b00000000_00000000_00001111_11000001; const zeroes: u32 = 0b00000000_00000000_00001111_11000001;
self.dtcm_size_base = value & ~zeroes; self.dtcm_size_base = value & ~zeroes;
const size_shamt: u5 = blk: { // const size_shamt: u5 = blk: {
const size = self.dtcm_size_base >> 1 & 0x1F; // const size = self.dtcm_size_base >> 1 & 0x1F;
if (size < 3) break :blk 3; // if (size < 3) break :blk 3;
if (size > 23) break :blk 23; // if (size > 23) break :blk 23;
break :blk @intCast(size); // break :blk @intCast(size);
}; // };
log.debug("DTCM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt}); // log.debug("DTCM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt});
log.debug("DTCM Region Base: 0x{X:0>8}", .{self.dtcm_size_base & 0xFFFF_F000}); // log.debug("DTCM Region Base: 0x{X:0>8}", .{self.dtcm_size_base & 0xFFFF_F000});
}, },
0b000_1001_0001_001 => { // Instruction TCM Size / Base 0b000_1001_0001_001 => { // Instruction TCM Size / Base
const zeroes: u32 = 0b00000000_00000000_00001111_11000001; const zeroes: u32 = 0b00000000_00000000_00001111_11000001;
@ -64,18 +101,19 @@ pub fn write(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void
self.itcm_size_base = value & ~(zeroes | itcm_specific); self.itcm_size_base = value & ~(zeroes | itcm_specific);
const size_shamt: u5 = blk: { // const size_shamt: u5 = blk: {
const size = self.dtcm_size_base >> 1 & 0x1F; // const size = self.dtcm_size_base >> 1 & 0x1F;
if (size < 3) break :blk 3; // if (size < 3) break :blk 3;
if (size > 23) break :blk 23; // if (size > 23) break :blk 23;
break :blk @intCast(size); // break :blk @intCast(size);
}; // };
log.debug("ICTM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt}); // log.debug("ICTM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt});
log.debug("ICTM Region Base: 0x{X:0>8}", .{0x0000_0000}); // log.debug("ICTM Region Base: 0x{X:0>8}", .{0x0000_0000});
}, },
else => _ = panic("TODO: implement write to register {}, c{}, c{}, {}", .{ op1, cn, cm, op2 }), else => _ = panic("TODO: implement write to register {}, c{}, c{}, {}", .{ op1, cn, cm, op2 }),
} }
} }
@ -97,6 +135,7 @@ pub fn reset(self: *@This()) void {
fn panic(comptime format: []const u8, args: anytype) u32 { fn panic(comptime format: []const u8, args: anytype) u32 {
log.err(format, args); log.err(format, args);
// @panic("Coprocessor invariant broken"); if (panic_on_unimplemented) @panic("cp15 invariant broken");
return 0; return 0;
} }