feat: implement IPCFIFO IRQs
turbo now passes rockwrestler!!!
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@ -1 +1 @@
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Subproject commit 8d2a3f1b672907abb5b1329df3e1e5c57dec0e71
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Subproject commit dcff3fd588af36cab270631ba83b47d9b27ec78c
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@ -82,6 +82,8 @@ pub fn loadFirm(allocator: Allocator, system: System, firm_path: []const u8) !vo
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const path = try std.mem.join(allocator, "/", &.{ firm_path, "bios9.bin" });
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defer allocator.free(path);
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log.debug("bios9 path: {s}", .{path});
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const file = try std.fs.cwd().openFile(path, .{});
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defer file.close();
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@ -7,10 +7,6 @@ const handleInterrupt = @import("emu.zig").handleInterrupt;
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const log = std.log.scoped(.shared_io);
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// FIXME: This whole thing is bad bad bad bad bad
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// I think only the IPC stuff needs to be here, since they talk to each other.
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// every other "shared I/O register" is just duplicated on both CPUs. So they shouldn't be here
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pub const Io = struct {
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/// Inter Process Communication FIFO
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ipc: Ipc = .{},
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@ -77,11 +73,11 @@ const Ipc = struct {
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if (value >> 3 & 1 == 1) {
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self._nds7.fifo.reset();
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self._nds7.cnt.send_fifo_empty.write(true);
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self._nds9.cnt.recv_fifo_empty.write(true);
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self._nds7.cnt.send_fifo_empty.set();
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self._nds9.cnt.recv_fifo_empty.set();
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self._nds7.cnt.send_fifo_full.write(false);
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self._nds9.cnt.recv_fifo_full.write(false);
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self._nds7.cnt.send_fifo_full.unset();
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self._nds9.cnt.recv_fifo_full.unset();
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}
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},
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.nds9 => {
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@ -98,11 +94,11 @@ const Ipc = struct {
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if (value >> 3 & 1 == 1) {
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self._nds9.fifo.reset();
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self._nds9.cnt.send_fifo_empty.write(true);
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self._nds7.cnt.recv_fifo_empty.write(true);
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self._nds9.cnt.send_fifo_empty.set();
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self._nds7.cnt.recv_fifo_empty.set();
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self._nds9.cnt.send_fifo_full.write(false);
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self._nds7.cnt.recv_fifo_full.write(false);
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self._nds9.cnt.send_fifo_full.unset();
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self._nds7.cnt.recv_fifo_full.unset();
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}
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},
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}
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@ -125,23 +121,49 @@ const Ipc = struct {
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if (!self._nds7.cnt.enable_fifos.read()) return;
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try self._nds7.fifo.push(value);
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const not_empty_cache = !self._nds9.cnt.recv_fifo_empty.read();
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// update status bits
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self._nds7.cnt.send_fifo_empty.write(self._nds7.fifo._len() == 0);
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self._nds9.cnt.recv_fifo_empty.write(self._nds7.fifo._len() == 0);
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self._nds7.cnt.send_fifo_full.write(self._nds7.fifo._len() == 0x10);
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self._nds9.cnt.recv_fifo_full.write(self._nds7.fifo._len() == 0x10);
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const not_empty = !self._nds9.cnt.recv_fifo_empty.read();
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if (self._nds9.cnt.recv_fifo_irq_enable.read() and !not_empty_cache and not_empty) {
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// NDS7 Send | NDS9 RECV (Handling Not Empty)
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const bus: *System.Bus9 = @ptrCast(@alignCast(self.arm946es.?.bus.ptr));
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bus.io.irq.ipc_recv_not_empty.set();
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handleInterrupt(.nds9, self.arm946es.?);
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}
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},
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.nds9 => {
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if (!self._nds9.cnt.enable_fifos.read()) return;
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try self._nds9.fifo.push(value);
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const not_empty_cache = !self._nds7.cnt.recv_fifo_empty.read();
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// update status bits
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self._nds9.cnt.send_fifo_empty.write(self._nds9.fifo._len() == 0);
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self._nds7.cnt.recv_fifo_empty.write(self._nds9.fifo._len() == 0);
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self._nds9.cnt.send_fifo_full.write(self._nds9.fifo._len() == 0x10);
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self._nds7.cnt.recv_fifo_full.write(self._nds9.fifo._len() == 0x10);
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const not_empty = !self._nds7.cnt.recv_fifo_empty.read();
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if (self._nds7.cnt.recv_fifo_irq_enable.read() and !not_empty_cache and not_empty) {
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// NDS9 Send | NDS7 RECV (Handling Not Empty)
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const bus: *System.Bus7 = @ptrCast(@alignCast(self.arm7tdmi.?.bus.ptr));
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bus.io.irq.ipc_recv_not_empty.set();
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handleInterrupt(.nds7, self.arm7tdmi.?);
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}
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},
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}
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}
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@ -162,6 +184,8 @@ const Ipc = struct {
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break :blk self._nds7.last_read orelse 0x0000_0000;
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};
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const empty_cache = self._nds9.cnt.send_fifo_empty.read();
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// update status bits
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self._nds7.cnt.recv_fifo_empty.write(self._nds9.fifo._len() == 0);
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self._nds9.cnt.send_fifo_empty.write(self._nds9.fifo._len() == 0);
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@ -169,6 +193,15 @@ const Ipc = struct {
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self._nds7.cnt.recv_fifo_full.write(self._nds9.fifo._len() == 0x10);
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self._nds9.cnt.send_fifo_full.write(self._nds9.fifo._len() == 0x10);
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const empty = self._nds9.cnt.send_fifo_empty.read();
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if (self._nds9.cnt.send_fifo_irq_enable.read() and (!empty_cache and empty)) {
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const bus: *System.Bus9 = @ptrCast(@alignCast(self.arm946es.?.bus.ptr));
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bus.io.irq.ipc_send_empty.set();
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handleInterrupt(.nds9, self.arm946es.?);
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}
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return value;
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},
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.nds9 => {
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@ -183,6 +216,8 @@ const Ipc = struct {
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break :blk self._nds7.last_read orelse 0x0000_0000;
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};
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const empty_cache = self._nds7.cnt.send_fifo_empty.read();
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// update status bits
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self._nds9.cnt.recv_fifo_empty.write(self._nds7.fifo._len() == 0);
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self._nds7.cnt.send_fifo_empty.write(self._nds7.fifo._len() == 0);
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@ -190,6 +225,15 @@ const Ipc = struct {
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self._nds9.cnt.recv_fifo_full.write(self._nds7.fifo._len() == 0x10);
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self._nds7.cnt.send_fifo_full.write(self._nds7.fifo._len() == 0x10);
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const empty = self._nds7.cnt.send_fifo_empty.read();
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if (self._nds7.cnt.send_fifo_irq_enable.read() and (!empty_cache and empty)) {
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const bus: *System.Bus7 = @ptrCast(@alignCast(self.arm7tdmi.?.bus.ptr));
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bus.io.irq.ipc_send_empty.set();
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handleInterrupt(.nds7, self.arm7tdmi.?);
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}
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return value;
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},
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}
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@ -263,7 +307,6 @@ pub const masks = struct {
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const err_mask: u32 = 0x4000; // bit 14
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const err_bit = (cnt & err_mask) & ~(value & err_mask);
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if (value & 0b1000 != 0) log.err("TODO: handle IPCFIFOCNT.3", .{});
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const without_err = (@as(u32, value) & _mask) | (cnt & ~_mask);
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return (without_err & ~err_mask) | err_bit;
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@ -278,6 +321,8 @@ pub const masks = struct {
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// FIXME: bitfields depends on NDS9 / NDS7
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pub const IntEnable = extern union {
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ipcsync: Bit(u32, 16),
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ipc_send_empty: Bit(u32, 17),
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ipc_recv_not_empty: Bit(u32, 18),
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raw: u32,
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};
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