feat: implement WRAM
This commit is contained in:
parent
e69bbde0e8
commit
79773782ca
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@ -1 +1 @@
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Subproject commit 481271ba2abcaab82b0930a10d424134099143c8
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Subproject commit 1bd96304badf24d50698e04abaf8f45c31571d6d
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135
src/core/emu.zig
135
src/core/emu.zig
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@ -96,33 +96,146 @@ pub const SharedContext = struct {
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io: *SharedIo,
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main: *[4 * MiB]u8,
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wram: *[32 * KiB]u8,
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wram: *Wram,
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pub fn init(allocator: Allocator) !@This() {
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const wram = try allocator.create(Wram);
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errdefer allocator.destroy(wram);
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try wram.init(allocator);
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const ctx = .{
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.io = try allocator.create(SharedIo),
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.io = blk: {
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const io = try allocator.create(SharedIo);
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io.* = .{};
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break :blk io;
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},
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.wram = wram,
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.main = try allocator.create([4 * MiB]u8),
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.wram = try allocator.create([32 * KiB]u8),
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};
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ctx.io.* = .{};
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return ctx;
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}
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pub fn deinit(self: @This(), allocator: Allocator) void {
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self.wram.deinit(allocator);
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allocator.destroy(self.wram);
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allocator.destroy(self.io);
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allocator.destroy(self.main);
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allocator.destroy(self.wram);
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}
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};
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// Before I implement Bus-wide Fastmem, Let's play with some more limited (read: less useful)
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// fastmem implementations
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// TODO: move somewhere else ideally
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pub const Wram = struct {
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const page_size = 1 * KiB; // perhaps too big?
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const addr_space_size = 0x8000;
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const table_len = addr_space_size / page_size;
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const IntFittingRange = std.math.IntFittingRange;
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const io = @import("io.zig");
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const KiB = 0x400;
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const log = std.log.scoped(.shared_wram);
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_buf: *[32 * KiB]u8,
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nds9_table: *const [table_len]?[*]u8,
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nds7_table: *const [table_len]?[*]u8,
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pub fn init(self: *@This(), allocator: Allocator) !void {
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const buf = try allocator.create([32 * KiB]u8);
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errdefer allocator.destroy(buf);
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const tables = try allocator.alloc(?[*]u8, 2 * table_len);
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@memset(tables, null);
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self.* = .{
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.nds9_table = tables[0..table_len],
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.nds7_table = tables[table_len .. 2 * table_len],
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._buf = buf,
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};
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}
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pub fn deinit(self: @This(), allocator: Allocator) void {
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allocator.destroy(self._buf);
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const ptr: [*]?[*]const u8 = @ptrCast(@constCast(self.nds9_table));
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allocator.free(ptr[0 .. 2 * table_len]);
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}
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pub fn update(self: *@This(), wramcnt: io.WramCnt) void {
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const mode = wramcnt.mode.read();
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const nds9_tbl = @constCast(self.nds9_table);
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const nds7_tbl = @constCast(self.nds7_table);
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for (nds9_tbl, nds7_tbl, 0..) |*nds9_ptr, *nds7_ptr, i| {
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const addr = i * page_size;
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switch (mode) {
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0b00 => {
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nds9_ptr.* = self._buf[addr..].ptr;
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nds7_ptr.* = null;
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},
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0b01 => {
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nds9_ptr.* = self._buf[0x4000 + (addr & 0x3FFF) ..].ptr;
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nds7_ptr.* = self._buf[(addr & 0x3FFF)..].ptr;
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},
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0b10 => {
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nds9_ptr.* = self._buf[(addr & 0x3FFF)..].ptr;
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nds7_ptr.* = self._buf[0x4000 + (addr & 0x3FFF) ..].ptr;
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},
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0b11 => {
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nds9_ptr.* = null;
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nds7_ptr.* = self._buf[addr..].ptr;
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},
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}
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}
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}
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// TODO: Rename
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const Device = enum { nds9, nds7 };
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pub fn read(self: @This(), comptime T: type, comptime dev: Device, address: u32) T {
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const page = address >> bits;
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const offset = address & (page_size - 1);
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const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
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if (table[page]) |some_ptr| {
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const ptr: [*]align(1) const T = @ptrCast(@alignCast(some_ptr));
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return ptr[offset / @sizeOf(T)];
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}
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log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(dev), T, 0x0300_0000 + address });
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return 0x00;
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}
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pub fn write(self: *@This(), comptime T: type, comptime dev: Device, address: u32, value: T) void {
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const page = address >> bits;
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const offset = address & (page_size - 1);
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const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
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if (table[page]) |some_ptr| {
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const ptr: [*]align(1) T = @ptrCast(@alignCast(some_ptr));
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ptr[offset / @sizeOf(T)] = value;
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return;
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}
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log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(dev), T, 0x0300_0000 + address, value });
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}
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};
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pub inline fn forceAlign(comptime T: type, address: u32) u32 {
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return switch (T) {
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u32 => address & ~@as(u32, 3),
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u16 => address & ~@as(u32, 1),
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u8 => address,
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else => @compileError("Bus: Invalid read/write type"),
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};
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return address & ~@as(u32, @sizeOf(T) - 1);
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}
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pub const System = struct {
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@ -35,6 +35,8 @@ pub const Io = struct {
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/// Caller must cast the `u8` to either `nds7.PostFlg` or `nds9.PostFlg`
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post_flg: u8 = @intFromEnum(nds7.PostFlag.in_progress),
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wramcnt: WramCnt = .{ .raw = 0x00 },
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// TODO: DS Cartridge I/O Ports
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};
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@ -74,10 +76,30 @@ const IpcFifo = struct {
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.nds7 => {
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self._nds7.sync.raw = masks.ipcFifoSync(self._nds7.sync.raw, value);
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self._nds9.sync.raw = masks.mask(self._nds9.sync.raw, (self._nds7.sync.raw >> 8) & 0xF, 0xF);
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if (value >> 3 & 1 == 1) {
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self._nds7.fifo.reset();
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self._nds7.cnt.send_fifo_empty.write(true);
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self._nds9.cnt.recv_fifo_empty.write(true);
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self._nds7.cnt.send_fifo_full.write(false);
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self._nds9.cnt.recv_fifo_full.write(false);
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}
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},
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.nds9 => {
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self._nds9.sync.raw = masks.ipcFifoSync(self._nds9.sync.raw, value);
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self._nds7.sync.raw = masks.mask(self._nds7.sync.raw, (self._nds9.sync.raw >> 8) & 0xF, 0xF);
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if (value >> 3 & 1 == 1) {
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self._nds9.fifo.reset();
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self._nds9.cnt.send_fifo_empty.write(true);
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self._nds7.cnt.recv_fifo_empty.write(true);
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self._nds9.cnt.send_fifo_full.write(false);
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self._nds7.cnt.recv_fifo_full.write(false);
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}
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},
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}
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}
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@ -218,6 +240,11 @@ const IpcFifoCnt = extern union {
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raw: u32,
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};
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pub const WramCnt = extern union {
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mode: Bitfield(u8, 0, 2),
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raw: u8,
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};
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pub const masks = struct {
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const Bus9 = @import("nds9/Bus.zig");
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const Bus7 = @import("nds7/Bus.zig");
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@ -4,6 +4,7 @@ const io = @import("io.zig");
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const Scheduler = @import("../Scheduler.zig");
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const SharedIo = @import("../io.zig").Io;
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const SharedContext = @import("../emu.zig").SharedContext;
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const Wram = @import("../emu.zig").Wram;
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const forceAlign = @import("../emu.zig").forceAlign;
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const Allocator = std.mem.Allocator;
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@ -16,6 +17,7 @@ const log = std.log.scoped(.nds7_bus);
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scheduler: *Scheduler,
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main: *[4 * MiB]u8,
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wram_shr: *Wram,
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wram: *[64 * KiB]u8,
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io: io.Io,
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@ -26,6 +28,7 @@ pub fn init(allocator: Allocator, scheduler: *Scheduler, shared_ctx: SharedConte
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return .{
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.main = shared_ctx.main,
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.wram_shr = shared_ctx.wram,
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.wram = wram,
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.scheduler = scheduler,
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.io = io.Io.init(shared_ctx.io),
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@ -60,6 +63,10 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
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return switch (aligned_addr) {
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0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
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0x0300_0000...0x037F_FFFF => switch (self.io.shared.wramcnt.mode.read()) {
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0b00 => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
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else => self.wram_shr.read(T, .nds7, address & 0x7FFF),
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},
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0x0380_0000...0x0380_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
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0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
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else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
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@ -88,6 +95,10 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
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switch (aligned_addr) {
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0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
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0x0300_0000...0x037F_FFFF => switch (self.io.shared.wramcnt.mode.read()) {
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0b00 => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
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else => self.wram_shr.write(T, .nds7, address & 0x7FFF, value),
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},
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0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
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0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
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else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),
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@ -33,6 +33,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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},
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u8 => switch (address) {
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0x0400_0241 => bus.io.shared.wramcnt.raw,
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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},
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else => @compileError(T ++ " is an unsupported bus read type"),
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@ -4,6 +4,7 @@ const io = @import("io.zig");
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const Ppu = @import("../ppu.zig").Ppu;
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const Scheduler = @import("../Scheduler.zig");
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const SharedContext = @import("../emu.zig").SharedContext;
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const Wram = @import("../emu.zig").Wram;
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const forceAlign = @import("../emu.zig").forceAlign;
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const Allocator = std.mem.Allocator;
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@ -15,7 +16,7 @@ const KiB = 0x400;
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const log = std.log.scoped(.nds9_bus);
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main: *[4 * MiB]u8,
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wram: *[32 * KiB]u8,
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wram: *Wram,
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vram1: *[512 * KiB]u8, // TODO: Rename
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io: io.Io,
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ppu: Ppu,
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@ -42,7 +43,6 @@ pub fn init(allocator: Allocator, scheduler: *Scheduler, shared_ctx: SharedConte
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pub fn deinit(self: *@This(), allocator: Allocator) void {
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self.ppu.deinit(allocator);
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allocator.destroy(self.vram1);
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}
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@ -73,7 +73,7 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
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return switch (aligned_addr) {
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0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
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// TODO: Impl Shared WRAM
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0x0300_0000...0x03FF_FFFF => self.wram.read(T, .nds9, aligned_addr & 0x7FFF),
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0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
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0x0600_0000...0x06FF_FFFF => readInt(T, self.vram1[aligned_addr & 0x0007_FFFF ..][0..byte_count]),
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else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
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@ -102,6 +102,7 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
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switch (aligned_addr) {
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0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
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0x0300_0000...0x03FF_FFFF => self.wram.write(T, .nds9, aligned_addr & 0x7FFF, value),
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0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
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0x0600_0000...0x06FF_FFFF => writeInt(T, self.vram1[aligned_addr & 0x0007_FFFF ..][0..byte_count], value),
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else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),
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@ -112,70 +113,3 @@ fn warn(comptime format: []const u8, args: anytype) u0 {
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log.warn(format, args);
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return 0;
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}
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// Before I implement Bus-wide Fastmem, Let's play with some more limited (read: less useful)
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// fastmem implementations
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const Wram = struct {
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const page_size = 1 * KiB; // perhaps too big?
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const addr_space_size = 0x0100_0000;
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const table_len = addr_space_size / page_size;
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const IntFittingRange = std.math.IntFittingRange;
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_ptr: *[32 * KiB]u8,
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read_table: *const [table_len]?*const anyopaque,
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write_table: *const [table_len]?*anyopaque,
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pub fn init(allocator: Allocator, ptr: *[32 * KiB]u8) @This() {
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const tables = try allocator.create(?*anyopaque, 2 * table_len);
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return .{
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.read_table = tables[0..table_len],
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.write_table = tables[table_len .. 2 * table_len],
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._ptr = ptr,
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};
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}
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pub fn update(_: *@This()) void {
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@panic("TODO: reload WRAM FASTMEM");
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}
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pub fn read(self: @This(), comptime T: type, address: u32) T {
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const page = address >> bits;
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const offset = address & (page_size - 1);
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std.debug.assert(page < table_len);
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if (self.read_table[page]) |some_ptr| {
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const ptr: [*]const T = @ptrCast(@alignCast(some_ptr));
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return ptr[forceAlign(T, offset) / @sizeOf(T)];
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}
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log.err("read(T: {}, addr: 0x{X:0>8}) was in un-mapped WRAM space", .{ T, address });
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return 0x00;
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}
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pub fn write(self: *@This(), comptime T: type, address: u32, value: T) void {
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const page = address >> bits;
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const offset = address & (page_size - 1);
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std.debug.assert(page < table_len);
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if (self.write_table[page]) |some_ptr| {
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const ptr: [*]T = @ptrCast(@alignCast(some_ptr));
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ptr[forceAlign(T, offset) / @sizeOf(T)] = value;
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return;
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}
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log.warn("write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped WRAM space", .{ T, address, value });
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}
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pub fn deinit(self: @This(), allocator: Allocator) void {
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const og_ptr: [*]?*anyopaque = @ptrCast(self.read_table);
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allocator.free(og_ptr[0 .. 2 * table_len]);
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}
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};
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@ -135,6 +135,10 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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0x0400_0241 => bus.ppu.io.vramcnt_b.raw = value,
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0x0400_0242 => bus.ppu.io.vramcnt_c.raw = value,
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0x0400_0243 => bus.ppu.io.vramcnt_d.raw = value,
|
||||
0x0400_0247 => {
|
||||
bus.io.shared.wramcnt.raw = value;
|
||||
bus.wram.update(bus.io.shared.wramcnt);
|
||||
},
|
||||
|
||||
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
|
||||
},
|
||||
|
|
|
|||
Loading…
Reference in New Issue