fix(nds): impl enough i/o to get ARM7WRESTLER booting
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37aff56c22
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64b1bdbe19
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@ -12,6 +12,9 @@ pub const Io = struct {
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ipc: Ipc = .{},
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wramcnt: WramCnt = .{ .raw = 0x00 },
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// Read Only
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keyinput: AtomicKeyInput = .{},
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};
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fn warn(comptime format: []const u8, args: anytype) u0 {
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@ -390,3 +393,41 @@ const Fifo = struct {
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return idx & _mask;
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}
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};
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/// Read Only
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/// 0 = Pressed, 1 = Released
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pub const KeyInput = extern union {
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a: Bit(u16, 0),
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b: Bit(u16, 1),
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select: Bit(u16, 2),
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start: Bit(u16, 3),
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right: Bit(u16, 4),
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left: Bit(u16, 5),
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up: Bit(u16, 6),
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down: Bit(u16, 7),
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shoulder_r: Bit(u16, 8),
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shoulder_l: Bit(u16, 9),
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raw: u16,
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};
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const AtomicKeyInput = struct {
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const Self = @This();
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const Ordering = std.atomic.Ordering;
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inner: KeyInput = .{ .raw = 0x03FF },
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pub inline fn load(self: *const Self, comptime ordering: Ordering) u16 {
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return switch (ordering) {
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.AcqRel, .Release => @compileError("not supported for atomic loads"),
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else => @atomicLoad(u16, &self.inner.raw, ordering),
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};
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}
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pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: Ordering) void {
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_ = @atomicRmw(u16, &self.inner.raw, .Or, value, ordering);
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}
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pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: Ordering) void {
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_ = @atomicRmw(u16, &self.inner.raw, .And, value, ordering);
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}
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};
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@ -3,6 +3,8 @@ const std = @import("std");
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const Bitfield = @import("bitfield").Bitfield;
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const Bit = @import("bitfield").Bit;
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const Ppu = @import("../ppu.zig").Ppu;
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const Bus = @import("Bus.zig");
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const SharedCtx = @import("../emu.zig").SharedCtx;
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const masks = @import("../io.zig").masks;
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@ -35,9 +37,15 @@ pub const Io = struct {
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/// Read/Write
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haltcnt: Haltcnt = .execute,
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ppu: ?*Ppu.Io = null,
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pub fn init(io: *SharedCtx.Io) @This() {
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return .{ .shr = io };
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}
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pub fn configure(self: *@This(), ppu: *Ppu) void {
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self.ppu = &ppu.io;
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}
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};
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pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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@ -58,12 +66,14 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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},
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u16 => switch (address) {
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0x0400_0004 => bus.io.ppu.?.nds7.dispstat.raw,
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// DMA Transfers
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0x0400_00B0...0x0400_00DE => warn("TODO: impl DMA", .{}),
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// Timers
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0x0400_0100...0x0400_010E => warn("TODO: impl timer", .{}),
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0x0400_0130 => bus.io.shr.keyinput.load(.Monotonic),
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0x0400_0180 => @truncate(bus.io.shr.ipc._nds7.sync.raw),
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0x0400_0184 => @truncate(bus.io.shr.ipc._nds7.cnt.raw),
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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@ -111,6 +121,8 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds7, value),
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0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds7, value),
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0x0400_0208 => bus.io.ime = value & 1 == 1,
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else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>4})", .{ T, address, value }),
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},
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u8 => switch (address) {
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@ -34,9 +34,6 @@ pub const Io = struct {
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/// Caller must cast the `u32` to either `nds7.IntRequest` or `nds9.IntRequest`
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irq: IntRequest = .{ .raw = 0x0000_0000 },
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// Read Only
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keyinput: AtomicKeyInput = .{},
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/// DS Maths
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div: Divisor = .{},
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sqrt: SquareRootUnit = .{},
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@ -65,9 +62,9 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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0x0400_02A8, 0x0400_02AC => @truncate(bus.io.div.remainder >> shift(u64, address)),
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0x0400_02B4 => @truncate(bus.io.sqrt.result),
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0x0400_4008 => 0x0000_0000, // Lets software know this is NOT a DSi
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0x0410_0000 => bus.io.shr.ipc.recv(.nds9),
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0x0400_4000, 0x0400_4008 => 0x0000_0000, // Lets software know this is NOT a DSi
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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},
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u16 => switch (address) {
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@ -79,7 +76,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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0x0400_0100...0x0400_010E => warn("TODO: impl timer", .{}),
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0x0400_0004 => bus.ppu.io.nds9.dispstat.raw,
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0x0400_0130 => bus.io.keyinput.load(.Monotonic),
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0x0400_0130 => bus.io.shr.keyinput.load(.Monotonic),
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0x0400_0180 => @truncate(bus.io.shr.ipc._nds9.sync.raw),
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0x0400_0184 => @truncate(bus.io.shr.ipc._nds9.cnt.raw),
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@ -97,6 +94,8 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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// Timers
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0x0400_0100...0x0400_010F => warn("TODO: impl timer", .{}),
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0x0400_0208 => @intFromBool(bus.io.ime),
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0x0400_4000 => 0x00, // Lets software know this is NOT a DSi
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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},
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@ -147,11 +146,16 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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bus.io.sqrt.schedule(bus.scheduler);
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},
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// Engine B
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0x0400_0304 => bus.ppu.io.powcnt.raw = value,
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0x0400_1000 => bus.ppu.engines[1].dispcnt.raw = value,
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else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
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},
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u16 => switch (address) {
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0x0400_0004 => bus.ppu.io.nds9.dispstat.raw = value,
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// DMA Transfers
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0x0400_00B0...0x0400_00DE => log.warn("TODO: impl DMA", .{}),
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0x0400_00E0...0x0400_00EE => log.warn("TODO: impl DMA fill", .{}),
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@ -185,6 +189,8 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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// Timers
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0x0400_0100...0x0400_010F => log.warn("TODO: impl timer", .{}),
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0x0400_0208 => bus.io.ime = value & 1 == 1,
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0x0400_0240 => {
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bus.ppu.vram.io.cnt_a.raw = value;
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bus.ppu.vram.update();
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@ -470,41 +476,3 @@ pub const Dispstat = extern union {
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lyc: Bitfield(u16, 7, 9),
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raw: u16,
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};
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/// Read Only
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/// 0 = Pressed, 1 = Released
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pub const KeyInput = extern union {
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a: Bit(u16, 0),
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b: Bit(u16, 1),
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select: Bit(u16, 2),
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start: Bit(u16, 3),
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right: Bit(u16, 4),
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left: Bit(u16, 5),
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up: Bit(u16, 6),
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down: Bit(u16, 7),
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shoulder_r: Bit(u16, 8),
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shoulder_l: Bit(u16, 9),
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raw: u16,
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};
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const AtomicKeyInput = struct {
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const Self = @This();
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const Ordering = std.atomic.Ordering;
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inner: KeyInput = .{ .raw = 0x03FF },
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pub inline fn load(self: *const Self, comptime ordering: Ordering) u16 {
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return switch (ordering) {
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.AcqRel, .Release => @compileError("not supported for atomic loads"),
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else => @atomicLoad(u16, &self.inner.raw, ordering),
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};
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}
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pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: Ordering) void {
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_ = @atomicRmw(u16, &self.inner.raw, .Or, value, ordering);
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}
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pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: Ordering) void {
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_ = @atomicRmw(u16, &self.inner.raw, .And, value, ordering);
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}
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};
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@ -29,13 +29,13 @@ pub const Ppu = struct {
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const ty = @import("nds9/io.zig");
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nds9: struct {
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dispstat: ty.Dispstat = .{ .raw = 0x0000_0000 },
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vcount: ty.Vcount = .{ .raw = 0x0000_0000 },
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dispstat: ty.Dispstat = .{ .raw = 0x00000 },
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vcount: ty.Vcount = .{ .raw = 0x0000 },
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} = .{},
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nds7: struct {
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dispstat: ty.Dispstat = .{ .raw = 0x0000_0000 },
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vcount: ty.Vcount = .{ .raw = 0x0000_0000 },
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dispstat: ty.Dispstat = .{ .raw = 0x0000 },
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vcount: ty.Vcount = .{ .raw = 0x00000 },
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} = .{},
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powcnt: ty.PowCnt = .{ .raw = 0x0000_0000 },
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@ -51,6 +51,9 @@ pub fn main() !void {
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var bus7 = try System.Bus7.init(allocator, &scheduler, ctx);
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var bus9 = try System.Bus9.init(allocator, &scheduler, ctx);
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// TODO: Think of a better way to do this
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bus7.io.configure(&bus9.ppu);
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var arm7tdmi = System.Arm7tdmi.init(IScheduler.init(&scheduler), IBus.init(&bus7));
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var arm946es = System.Arm946es.init(IScheduler.init(&scheduler), IBus.init(&bus9), ICoprocessor.init(&cp15));
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@ -8,7 +8,7 @@ const imgui = @import("ui/imgui.zig");
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const emu = @import("core/emu.zig");
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const System = @import("core/emu.zig").System;
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const KeyInput = @import("core/nds9/io.zig").KeyInput;
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const KeyInput = @import("core/io.zig").KeyInput;
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const Scheduler = @import("core/Scheduler.zig");
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const Allocator = std.mem.Allocator;
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@ -141,7 +141,7 @@ pub const Ui = struct {
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else => {},
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}
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system.bus9.io.keyinput.fetchAnd(~keyinput.raw, .Monotonic);
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system.bus9.io.shr.keyinput.fetchAnd(~keyinput.raw, .Monotonic);
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},
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SDL.SDL_KEYUP => {
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// TODO: Make use of compare_and_xor?
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@ -162,7 +162,7 @@ pub const Ui = struct {
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else => {},
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}
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system.bus9.io.keyinput.fetchOr(keyinput.raw, .Monotonic);
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system.bus9.io.shr.keyinput.fetchOr(keyinput.raw, .Monotonic);
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},
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else => {},
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}
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