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feat: implement VRAM allocation

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This commit is contained in:
Rekai Nyangadzayi Musuka
2023-10-03 00:32:32 -05:00
parent 77caa9ae52
commit 3a35c5b428
6 changed files with 422 additions and 50 deletions
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9
src/core/nds7/Bus.zig
View File

@@ -5,6 +5,7 @@ const Scheduler = @import("../Scheduler.zig");
const SharedIo = @import("../io.zig").Io;
const SharedContext = @import("../emu.zig").SharedContext;
const Wram = @import("../emu.zig").Wram;
const Vram = @import("../ppu.zig").Vram;
const forceAlign = @import("../emu.zig").forceAlign;
const Allocator = std.mem.Allocator;
@@ -19,6 +20,7 @@ scheduler: *Scheduler,
main: *[4 * MiB]u8,
wram_shr: *Wram,
wram: *[64 * KiB]u8,
vram: *Vram,
io: io.Io,
pub fn init(allocator: Allocator, scheduler: *Scheduler, shared_ctx: SharedContext) !@This() {
@@ -29,6 +31,7 @@ pub fn init(allocator: Allocator, scheduler: *Scheduler, shared_ctx: SharedConte
return .{
.main = shared_ctx.main,
.wram_shr = shared_ctx.wram,
.vram = shared_ctx.vram,
.wram = wram,
.scheduler = scheduler,
.io = io.Io.init(shared_ctx.io),
@@ -65,10 +68,11 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
0x0300_0000...0x037F_FFFF => switch (self.io.shared.wramcnt.mode.read()) {
0b00 => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
else => self.wram_shr.read(T, .nds7, address & 0x7FFF),
else => self.wram_shr.read(T, .nds7, aligned_addr),
},
0x0380_0000...0x0380_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
0x0600_0000...0x06FF_FFFF => self.vram.read(T, .nds7, aligned_addr),
else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
};
}
@@ -97,10 +101,11 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
0x0300_0000...0x037F_FFFF => switch (self.io.shared.wramcnt.mode.read()) {
0b00 => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
else => self.wram_shr.write(T, .nds7, address & 0x7FFF, value),
else => self.wram_shr.write(T, .nds7, aligned_addr, value),
},
0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
0x0600_0000...0x06FF_FFFF => self.vram.write(T, .nds7, aligned_addr, value),
else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),
}
}

7
src/core/nds7/io.zig
View File

@@ -33,6 +33,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
},
u8 => switch (address) {
0x0400_0240 => bus.vram.stat().raw,
0x0400_0241 => bus.io.shared.wramcnt.raw,
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
},
@@ -66,3 +67,9 @@ fn warn(comptime format: []const u8, args: anytype) u0 {
log.warn(format, args);
return 0;
}
pub const Vramstat = extern union {
vramc_enabled: Bit(u8, 0),
vramd_enabled: Bit(u8, 1),
raw: u8,
};