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chore: unify "enum { nds7, nds9 }"s

This commit is contained in:
Rekai Nyangadzayi Musuka 2023-11-22 00:19:37 -06:00
parent 16233f3cd8
commit 3a1ebfb6e6
3 changed files with 42 additions and 34 deletions
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41
src/core/emu.zig
View File

@ -270,15 +270,12 @@ pub const Wram = struct {
}
}
// TODO: Rename
const Device = enum { nds9, nds7 };
pub fn read(self: @This(), comptime T: type, comptime dev: Device, address: u32) T {
pub fn read(self: @This(), comptime T: type, comptime proc: System.Process, address: u32) T {
const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
const masked_addr = address & (addr_space_size - 1);
const page = masked_addr >> bits;
const offset = masked_addr & (page_size - 1);
const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
if (table[page]) |some_ptr| {
const ptr: [*]const T = @ptrCast(@alignCast(some_ptr));
@ -286,16 +283,16 @@ pub const Wram = struct {
return ptr[offset / @sizeOf(T)];
}
log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(dev), T, 0x0300_0000 + address });
log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(proc), T, 0x0300_0000 + address });
return 0x00;
}
pub fn write(self: *@This(), comptime T: type, comptime dev: Device, address: u32, value: T) void {
pub fn write(self: *@This(), comptime T: type, comptime proc: System.Process, address: u32, value: T) void {
const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
const masked_addr = address & (addr_space_size - 1);
const page = masked_addr >> bits;
const offset = masked_addr & (page_size - 1);
const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
if (table[page]) |some_ptr| {
const ptr: [*]T = @ptrCast(@alignCast(some_ptr));
@ -304,7 +301,7 @@ pub const Wram = struct {
return;
}
log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(dev), T, 0x0300_0000 + address, value });
log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(proc), T, 0x0300_0000 + address, value });
}
};
@ -320,6 +317,8 @@ pub const System = struct {
pub const Arm7tdmi = @import("arm32").Arm7tdmi;
pub const Arm946es = @import("arm32").Arm946es;
pub const Process = enum { nds7, nds9 };
arm7tdmi: *Arm7tdmi,
arm946es: *Arm946es,
@ -332,17 +331,29 @@ pub const System = struct {
self.bus7.deinit(allocator);
self.bus9.deinit(allocator);
}
fn Cpu(comptime proc: Process) type {
return switch (proc) {
.nds7 => Arm7tdmi,
.nds9 => Arm946es,
};
}
fn Bus(comptime proc: Process) type {
return switch (proc) {
.nds7 => Bus7,
.nds9 => Bus9,
};
}
};
// FIXME: Using Wram.Device here is jank. System should probably carry an Enum + some Generic Type Fns
pub fn handleInterrupt(comptime dev: Wram.Device, cpu: if (dev == .nds9) *System.Arm946es else *System.Arm7tdmi) void {
const Bus = if (dev == .nds9) System.Bus9 else System.Bus7;
const bus_ptr: *Bus = @ptrCast(@alignCast(cpu.bus.ptr));
pub fn handleInterrupt(comptime proc: System.Process, cpu: *System.Cpu(proc)) void {
const bus_ptr: *System.Bus(proc) = @ptrCast(@alignCast(cpu.bus.ptr));
if (!bus_ptr.io.ime or cpu.cpsr.i.read()) return; // ensure irqs are enabled
if ((bus_ptr.io.ie.raw & bus_ptr.io.irq.raw) == 0) return; // ensure there is an irq to handle
switch (dev) {
switch (proc) {
.nds9 => {
const cp15: *System.Cp15 = @ptrCast(@alignCast(cpu.cp15.ptr));
cp15.wait_for_interrupt = false;
@ -359,6 +370,6 @@ pub fn handleInterrupt(comptime dev: Wram.Device, cpu: if (dev == .nds9) *System
cpu.r[14] = ret_addr;
cpu.spsr.raw = spsr.raw;
cpu.r[15] = if (dev == .nds9) 0xFFFF_0018 else 0x0000_0018;
cpu.r[15] = if (proc == .nds9) 0xFFFF_0018 else 0x0000_0018;
cpu.pipe.reload(cpu);
}

18
src/core/io.zig
View File

@ -36,8 +36,6 @@ const Ipc = struct {
// TODO: DS Cartridge I/O Ports
const Source = enum { nds7, nds9 };
const Impl = struct {
/// IPC Synchronize
/// Read/Write
@ -60,8 +58,8 @@ const Ipc = struct {
/// IPCSYNC
/// Read/Write
pub fn setIpcSync(self: *@This(), comptime src: Source, value: anytype) void {
switch (src) {
pub fn setIpcSync(self: *@This(), comptime proc: System.Process, value: anytype) void {
switch (proc) {
.nds7 => {
self._nds7.sync.raw = masks.ipcFifoSync(self._nds7.sync.raw, value);
self._nds9.sync.raw = masks.mask(self._nds9.sync.raw, (self._nds7.sync.raw >> 8) & 0xF, 0xF);
@ -109,8 +107,8 @@ const Ipc = struct {
/// IPCFIFOCNT
/// Read/Write
pub fn setIpcFifoCnt(self: *@This(), comptime src: Source, value: anytype) void {
switch (src) {
pub fn setIpcFifoCnt(self: *@This(), comptime proc: System.Process, value: anytype) void {
switch (proc) {
.nds7 => self._nds7.cnt.raw = masks.ipcFifoCnt(self._nds7.cnt.raw, value),
.nds9 => self._nds9.cnt.raw = masks.ipcFifoCnt(self._nds9.cnt.raw, value),
}
@ -118,8 +116,8 @@ const Ipc = struct {
/// IPC Send FIFO
/// Write-Only
pub fn send(self: *@This(), comptime src: Source, value: u32) void {
switch (src) {
pub fn send(self: *@This(), comptime proc: System.Process, value: u32) void {
switch (proc) {
.nds7 => {
if (!self._nds7.cnt.enable_fifos.read()) return;
self._nds7.fifo.push(value) catch unreachable; // see early return above
@ -173,8 +171,8 @@ const Ipc = struct {
/// IPC Receive FIFO
/// Read-Only
pub fn recv(self: *@This(), comptime src: Source) u32 {
switch (src) {
pub fn recv(self: *@This(), comptime proc: System.Process) u32 {
switch (proc) {
.nds7 => {
const enabled = self._nds7.cnt.enable_fifos.read();
const val_opt = if (enabled) self._nds9.fifo.pop() else self._nds9.fifo.peek();

17
src/core/ppu/Vram.zig
View File

@ -1,6 +1,8 @@
const std = @import("std");
const KiB = 0x400;
const System = @import("../emu.zig").System;
const Allocator = std.mem.Allocator;
const IntFittingRange = std.math.IntFittingRange;
@ -253,15 +255,12 @@ pub fn update(self: *@This()) void {
}
}
// TODO: Rename
const Device = enum { nds9, nds7 };
pub fn read(self: @This(), comptime T: type, comptime dev: Device, address: u32) T {
pub fn read(self: @This(), comptime T: type, comptime proc: System.Process, address: u32) T {
const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
const masked_addr = address & (addr_space_size - 1);
const page = masked_addr >> bits;
const offset = masked_addr & (page_size - 1);
const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
if (table[page]) |some_ptr| {
const ptr: [*]const T = @ptrCast(@alignCast(some_ptr));
@ -269,16 +268,16 @@ pub fn read(self: @This(), comptime T: type, comptime dev: Device, address: u32)
return ptr[offset / @sizeOf(T)];
}
log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped VRAM space", .{ @tagName(dev), T, address });
log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped VRAM space", .{ @tagName(proc), T, address });
return 0x00;
}
pub fn write(self: *@This(), comptime T: type, comptime dev: Device, address: u32, value: T) void {
pub fn write(self: *@This(), comptime T: type, comptime proc: System.Process, address: u32, value: T) void {
const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
const masked_addr = address & (addr_space_size - 1);
const page = masked_addr >> bits;
const offset = masked_addr & (page_size - 1);
const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
if (table[page]) |some_ptr| {
const ptr: [*]T = @ptrCast(@alignCast(some_ptr));
@ -287,5 +286,5 @@ pub fn write(self: *@This(), comptime T: type, comptime dev: Device, address: u3
return;
}
log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped VRA< space", .{ @tagName(dev), T, address, value });
log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped VRA< space", .{ @tagName(proc), T, address, value });
}