chore: unify "enum { nds7, nds9 }"s
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16233f3cd8
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3a1ebfb6e6
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@ -270,15 +270,12 @@ pub const Wram = struct {
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}
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}
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}
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}
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// TODO: Rename
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pub fn read(self: @This(), comptime T: type, comptime proc: System.Process, address: u32) T {
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const Device = enum { nds9, nds7 };
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pub fn read(self: @This(), comptime T: type, comptime dev: Device, address: u32) T {
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const masked_addr = address & (addr_space_size - 1);
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const masked_addr = address & (addr_space_size - 1);
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const page = masked_addr >> bits;
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const page = masked_addr >> bits;
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const offset = masked_addr & (page_size - 1);
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const offset = masked_addr & (page_size - 1);
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const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
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const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
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if (table[page]) |some_ptr| {
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if (table[page]) |some_ptr| {
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const ptr: [*]const T = @ptrCast(@alignCast(some_ptr));
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const ptr: [*]const T = @ptrCast(@alignCast(some_ptr));
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@ -286,16 +283,16 @@ pub const Wram = struct {
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return ptr[offset / @sizeOf(T)];
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return ptr[offset / @sizeOf(T)];
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}
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}
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log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(dev), T, 0x0300_0000 + address });
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log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(proc), T, 0x0300_0000 + address });
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return 0x00;
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return 0x00;
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}
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}
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pub fn write(self: *@This(), comptime T: type, comptime dev: Device, address: u32, value: T) void {
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pub fn write(self: *@This(), comptime T: type, comptime proc: System.Process, address: u32, value: T) void {
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const masked_addr = address & (addr_space_size - 1);
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const masked_addr = address & (addr_space_size - 1);
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const page = masked_addr >> bits;
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const page = masked_addr >> bits;
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const offset = masked_addr & (page_size - 1);
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const offset = masked_addr & (page_size - 1);
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const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
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const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
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if (table[page]) |some_ptr| {
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if (table[page]) |some_ptr| {
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const ptr: [*]T = @ptrCast(@alignCast(some_ptr));
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const ptr: [*]T = @ptrCast(@alignCast(some_ptr));
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@ -304,7 +301,7 @@ pub const Wram = struct {
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return;
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return;
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}
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}
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log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(dev), T, 0x0300_0000 + address, value });
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log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(proc), T, 0x0300_0000 + address, value });
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}
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}
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};
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};
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@ -320,6 +317,8 @@ pub const System = struct {
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pub const Arm7tdmi = @import("arm32").Arm7tdmi;
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pub const Arm7tdmi = @import("arm32").Arm7tdmi;
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pub const Arm946es = @import("arm32").Arm946es;
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pub const Arm946es = @import("arm32").Arm946es;
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pub const Process = enum { nds7, nds9 };
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arm7tdmi: *Arm7tdmi,
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arm7tdmi: *Arm7tdmi,
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arm946es: *Arm946es,
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arm946es: *Arm946es,
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@ -332,17 +331,29 @@ pub const System = struct {
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self.bus7.deinit(allocator);
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self.bus7.deinit(allocator);
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self.bus9.deinit(allocator);
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self.bus9.deinit(allocator);
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}
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}
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fn Cpu(comptime proc: Process) type {
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return switch (proc) {
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.nds7 => Arm7tdmi,
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.nds9 => Arm946es,
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};
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}
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fn Bus(comptime proc: Process) type {
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return switch (proc) {
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.nds7 => Bus7,
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.nds9 => Bus9,
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};
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}
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};
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};
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// FIXME: Using Wram.Device here is jank. System should probably carry an Enum + some Generic Type Fns
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pub fn handleInterrupt(comptime proc: System.Process, cpu: *System.Cpu(proc)) void {
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pub fn handleInterrupt(comptime dev: Wram.Device, cpu: if (dev == .nds9) *System.Arm946es else *System.Arm7tdmi) void {
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const bus_ptr: *System.Bus(proc) = @ptrCast(@alignCast(cpu.bus.ptr));
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const Bus = if (dev == .nds9) System.Bus9 else System.Bus7;
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const bus_ptr: *Bus = @ptrCast(@alignCast(cpu.bus.ptr));
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if (!bus_ptr.io.ime or cpu.cpsr.i.read()) return; // ensure irqs are enabled
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if (!bus_ptr.io.ime or cpu.cpsr.i.read()) return; // ensure irqs are enabled
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if ((bus_ptr.io.ie.raw & bus_ptr.io.irq.raw) == 0) return; // ensure there is an irq to handle
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if ((bus_ptr.io.ie.raw & bus_ptr.io.irq.raw) == 0) return; // ensure there is an irq to handle
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switch (dev) {
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switch (proc) {
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.nds9 => {
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.nds9 => {
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const cp15: *System.Cp15 = @ptrCast(@alignCast(cpu.cp15.ptr));
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const cp15: *System.Cp15 = @ptrCast(@alignCast(cpu.cp15.ptr));
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cp15.wait_for_interrupt = false;
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cp15.wait_for_interrupt = false;
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@ -359,6 +370,6 @@ pub fn handleInterrupt(comptime dev: Wram.Device, cpu: if (dev == .nds9) *System
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cpu.r[14] = ret_addr;
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cpu.r[14] = ret_addr;
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cpu.spsr.raw = spsr.raw;
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cpu.spsr.raw = spsr.raw;
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cpu.r[15] = if (dev == .nds9) 0xFFFF_0018 else 0x0000_0018;
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cpu.r[15] = if (proc == .nds9) 0xFFFF_0018 else 0x0000_0018;
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cpu.pipe.reload(cpu);
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cpu.pipe.reload(cpu);
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}
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}
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@ -36,8 +36,6 @@ const Ipc = struct {
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// TODO: DS Cartridge I/O Ports
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// TODO: DS Cartridge I/O Ports
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const Source = enum { nds7, nds9 };
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const Impl = struct {
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const Impl = struct {
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/// IPC Synchronize
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/// IPC Synchronize
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/// Read/Write
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/// Read/Write
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@ -60,8 +58,8 @@ const Ipc = struct {
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/// IPCSYNC
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/// IPCSYNC
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/// Read/Write
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/// Read/Write
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pub fn setIpcSync(self: *@This(), comptime src: Source, value: anytype) void {
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pub fn setIpcSync(self: *@This(), comptime proc: System.Process, value: anytype) void {
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switch (src) {
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switch (proc) {
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.nds7 => {
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.nds7 => {
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self._nds7.sync.raw = masks.ipcFifoSync(self._nds7.sync.raw, value);
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self._nds7.sync.raw = masks.ipcFifoSync(self._nds7.sync.raw, value);
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self._nds9.sync.raw = masks.mask(self._nds9.sync.raw, (self._nds7.sync.raw >> 8) & 0xF, 0xF);
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self._nds9.sync.raw = masks.mask(self._nds9.sync.raw, (self._nds7.sync.raw >> 8) & 0xF, 0xF);
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@ -109,8 +107,8 @@ const Ipc = struct {
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/// IPCFIFOCNT
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/// IPCFIFOCNT
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/// Read/Write
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/// Read/Write
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pub fn setIpcFifoCnt(self: *@This(), comptime src: Source, value: anytype) void {
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pub fn setIpcFifoCnt(self: *@This(), comptime proc: System.Process, value: anytype) void {
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switch (src) {
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switch (proc) {
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.nds7 => self._nds7.cnt.raw = masks.ipcFifoCnt(self._nds7.cnt.raw, value),
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.nds7 => self._nds7.cnt.raw = masks.ipcFifoCnt(self._nds7.cnt.raw, value),
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.nds9 => self._nds9.cnt.raw = masks.ipcFifoCnt(self._nds9.cnt.raw, value),
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.nds9 => self._nds9.cnt.raw = masks.ipcFifoCnt(self._nds9.cnt.raw, value),
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}
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}
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@ -118,8 +116,8 @@ const Ipc = struct {
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/// IPC Send FIFO
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/// IPC Send FIFO
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/// Write-Only
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/// Write-Only
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pub fn send(self: *@This(), comptime src: Source, value: u32) void {
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pub fn send(self: *@This(), comptime proc: System.Process, value: u32) void {
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switch (src) {
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switch (proc) {
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.nds7 => {
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.nds7 => {
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if (!self._nds7.cnt.enable_fifos.read()) return;
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if (!self._nds7.cnt.enable_fifos.read()) return;
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self._nds7.fifo.push(value) catch unreachable; // see early return above
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self._nds7.fifo.push(value) catch unreachable; // see early return above
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@ -173,8 +171,8 @@ const Ipc = struct {
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/// IPC Receive FIFO
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/// IPC Receive FIFO
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/// Read-Only
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/// Read-Only
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pub fn recv(self: *@This(), comptime src: Source) u32 {
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pub fn recv(self: *@This(), comptime proc: System.Process) u32 {
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switch (src) {
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switch (proc) {
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.nds7 => {
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.nds7 => {
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const enabled = self._nds7.cnt.enable_fifos.read();
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const enabled = self._nds7.cnt.enable_fifos.read();
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const val_opt = if (enabled) self._nds9.fifo.pop() else self._nds9.fifo.peek();
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const val_opt = if (enabled) self._nds9.fifo.pop() else self._nds9.fifo.peek();
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@ -1,6 +1,8 @@
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const std = @import("std");
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const std = @import("std");
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const KiB = 0x400;
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const KiB = 0x400;
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const System = @import("../emu.zig").System;
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const Allocator = std.mem.Allocator;
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const Allocator = std.mem.Allocator;
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const IntFittingRange = std.math.IntFittingRange;
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const IntFittingRange = std.math.IntFittingRange;
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@ -253,15 +255,12 @@ pub fn update(self: *@This()) void {
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}
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}
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}
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}
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// TODO: Rename
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pub fn read(self: @This(), comptime T: type, comptime proc: System.Process, address: u32) T {
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const Device = enum { nds9, nds7 };
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pub fn read(self: @This(), comptime T: type, comptime dev: Device, address: u32) T {
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const masked_addr = address & (addr_space_size - 1);
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const masked_addr = address & (addr_space_size - 1);
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const page = masked_addr >> bits;
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const page = masked_addr >> bits;
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const offset = masked_addr & (page_size - 1);
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const offset = masked_addr & (page_size - 1);
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const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
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const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
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if (table[page]) |some_ptr| {
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if (table[page]) |some_ptr| {
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const ptr: [*]const T = @ptrCast(@alignCast(some_ptr));
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const ptr: [*]const T = @ptrCast(@alignCast(some_ptr));
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@ -269,16 +268,16 @@ pub fn read(self: @This(), comptime T: type, comptime dev: Device, address: u32)
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return ptr[offset / @sizeOf(T)];
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return ptr[offset / @sizeOf(T)];
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}
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}
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log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped VRAM space", .{ @tagName(dev), T, address });
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log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped VRAM space", .{ @tagName(proc), T, address });
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return 0x00;
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return 0x00;
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}
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}
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pub fn write(self: *@This(), comptime T: type, comptime dev: Device, address: u32, value: T) void {
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pub fn write(self: *@This(), comptime T: type, comptime proc: System.Process, address: u32, value: T) void {
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const masked_addr = address & (addr_space_size - 1);
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const masked_addr = address & (addr_space_size - 1);
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const page = masked_addr >> bits;
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const page = masked_addr >> bits;
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const offset = masked_addr & (page_size - 1);
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const offset = masked_addr & (page_size - 1);
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const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
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const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
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if (table[page]) |some_ptr| {
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if (table[page]) |some_ptr| {
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const ptr: [*]T = @ptrCast(@alignCast(some_ptr));
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const ptr: [*]T = @ptrCast(@alignCast(some_ptr));
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@ -287,5 +286,5 @@ pub fn write(self: *@This(), comptime T: type, comptime dev: Device, address: u3
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return;
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return;
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}
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}
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log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped VRA< space", .{ @tagName(dev), T, address, value });
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log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped VRA< space", .{ @tagName(proc), T, address, value });
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}
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}
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