chore(bus): force align writes to NDS7/NDS9 Bus
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parent
cd3a3dbe63
commit
1fc1f5782b
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@ -1 +1 @@
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Subproject commit ada2a08516d55a61bddd96f1c29e1547d0466049
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Subproject commit 591352a65b0ddbd5648f36910ae1ec899fed668d
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@ -131,3 +131,12 @@ pub const SharedContext = struct {
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allocator.destroy(self.main);
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allocator.destroy(self.main);
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}
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}
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};
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};
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pub inline fn forceAlign(comptime T: type, address: u32) u32 {
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return switch (T) {
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u32 => address & ~@as(u32, 3),
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u16 => address & ~@as(u32, 1),
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u8 => address,
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else => @compileError("Bus: Invalid read/write type"),
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};
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}
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@ -1,10 +1,10 @@
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const std = @import("std");
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const std = @import("std");
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const io = @import("io.zig");
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const io = @import("io.zig");
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const Scheduler = @import("Scheduler.zig");
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const Scheduler = @import("Scheduler.zig");
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const SharedIo = @import("../io.zig").Io;
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const SharedIo = @import("../io.zig").Io;
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const SharedContext = @import("../emu.zig").SharedContext;
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const SharedContext = @import("../emu.zig").SharedContext;
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const forceAlign = @import("../emu.zig").forceAlign;
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const Allocator = std.mem.Allocator;
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const Allocator = std.mem.Allocator;
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@ -50,17 +50,19 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
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const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
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const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
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const readInt = std.mem.readIntLittle;
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const readInt = std.mem.readIntLittle;
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const aligned_addr = forceAlign(T, address);
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switch (mode) {
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switch (mode) {
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// .debug => log.debug("read {} from 0x{X:0>8}", .{ T, address }),
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// .debug => log.debug("read {} from 0x{X:0>8}", .{ T, aligned_addr }),
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.debug => {},
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.debug => {},
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else => self.scheduler.tick += 1,
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else => self.scheduler.tick += 1,
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}
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}
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return switch (address) {
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return switch (aligned_addr) {
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0x0200_0000...0x02FF_FFFF => readInt(T, self.main[address & 0x003F_FFFF ..][0..byte_count]),
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0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
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0x0380_0000...0x0380_FFFF => readInt(T, self.wram[address & 0x0000_FFFF ..][0..byte_count]),
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0x0380_0000...0x0380_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
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0x0400_0000...0x04FF_FFFF => io.read(self, T, address),
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0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
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else => warn("unexpected read: 0x{x:0>8} -> {}", .{ address, T }),
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else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
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};
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};
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}
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}
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@ -76,17 +78,19 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
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const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
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const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
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const writeInt = std.mem.writeIntLittle;
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const writeInt = std.mem.writeIntLittle;
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const aligned_addr = forceAlign(T, address);
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switch (mode) {
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switch (mode) {
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// .debug => log.debug("wrote 0x{X:}{} to 0x{X:0>8}", .{ value, T, address }),
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// .debug => log.debug("wrote 0x{X:}{} to 0x{X:0>8}", .{ value, T, aligned_addr }),
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.debug => {},
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.debug => {},
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else => self.scheduler.tick += 1,
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else => self.scheduler.tick += 1,
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}
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}
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switch (address) {
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switch (aligned_addr) {
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0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[address & 0x003F_FFFF ..][0..byte_count], value),
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0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
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0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[address & 0x0000_FFFF ..][0..byte_count], value),
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0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
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0x0400_0000...0x04FF_FFFF => io.write(self, T, address, value),
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0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
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else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, address }),
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else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),
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}
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}
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}
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}
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@ -1,9 +1,10 @@
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const std = @import("std");
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const std = @import("std");
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const io = @import("io.zig");
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const Ppu = @import("../ppu.zig").Ppu;
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const Ppu = @import("../ppu.zig").Ppu;
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const Scheduler = @import("Scheduler.zig");
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const Scheduler = @import("Scheduler.zig");
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const SharedContext = @import("../emu.zig").SharedContext;
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const SharedContext = @import("../emu.zig").SharedContext;
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const io = @import("io.zig");
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const forceAlign = @import("../emu.zig").forceAlign;
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const Allocator = std.mem.Allocator;
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const Allocator = std.mem.Allocator;
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@ -60,17 +61,19 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
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const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
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const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
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const readInt = std.mem.readIntLittle;
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const readInt = std.mem.readIntLittle;
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const aligned_addr = forceAlign(T, address);
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switch (mode) {
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switch (mode) {
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// .debug => log.debug("read {} from 0x{X:0>8}", .{ T, address }),
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// .debug => log.debug("read {} from 0x{X:0>8}", .{ T, aligned_addr }),
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.debug => {},
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.debug => {},
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else => self.scheduler.tick += 1,
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else => self.scheduler.tick += 1,
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}
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}
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return switch (address) {
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return switch (aligned_addr) {
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0x0200_0000...0x02FF_FFFF => readInt(T, self.main[address & 0x003F_FFFF ..][0..byte_count]),
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0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
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0x0400_0000...0x04FF_FFFF => io.read(self, T, address),
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0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
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0x0600_0000...0x06FF_FFFF => readInt(T, self.vram1[address & 0x0007_FFFF ..][0..byte_count]),
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0x0600_0000...0x06FF_FFFF => readInt(T, self.vram1[aligned_addr & 0x0007_FFFF ..][0..byte_count]),
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else => warn("unexpected read: 0x{x:0>8} -> {}", .{ address, T }),
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else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
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};
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};
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}
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}
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@ -86,17 +89,19 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
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const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
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const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
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const writeInt = std.mem.writeIntLittle;
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const writeInt = std.mem.writeIntLittle;
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const aligned_addr = forceAlign(T, address);
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switch (mode) {
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switch (mode) {
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// .debug => log.debug("wrote 0x{X:}{} to 0x{X:0>8}", .{ value, T, address }),
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// .debug => log.debug("wrote 0x{X:}{} to 0x{X:0>8}", .{ value, T, aligned_addr }),
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.debug => {},
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.debug => {},
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else => self.scheduler.tick += 1,
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else => self.scheduler.tick += 1,
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}
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}
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switch (address) {
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switch (aligned_addr) {
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0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[address & 0x003F_FFFF ..][0..byte_count], value),
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0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
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0x0400_0000...0x04FF_FFFF => io.write(self, T, address, value),
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0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
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0x0600_0000...0x06FF_FFFF => writeInt(T, self.vram1[address & 0x0007_FFFF ..][0..byte_count], value),
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0x0600_0000...0x06FF_FFFF => writeInt(T, self.vram1[aligned_addr & 0x0007_FFFF ..][0..byte_count], value),
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else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, address }),
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else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),
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}
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}
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}
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}
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