feat(ppu): introduce concept of 2 graphics engines + refactor
This commit is contained in:
291
src/core/ppu/Vram.zig
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291
src/core/ppu/Vram.zig
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@@ -0,0 +1,291 @@
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const std = @import("std");
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const KiB = 0x400;
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const Allocator = std.mem.Allocator;
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const IntFittingRange = std.math.IntFittingRange;
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const page_size = 16 * KiB; // smallest allocation is 16 KiB
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const addr_space_size = 0x0100_0000; // 0x0600_0000 -> 0x06FF_FFFF (inclusive)
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const table_len = addr_space_size / page_size;
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const buf_len = 656 * KiB;
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const log = std.log.scoped(.vram);
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io: Io = .{},
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_buf: *[buf_len]u8,
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nds9_table: *const [table_len]?[*]u8,
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nds7_table: *const [table_len]?[*]u8,
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const Io = struct {
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pub const Vramstat = nds7.Vramstat;
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const nds9 = @import("../nds9/io.zig");
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const nds7 = @import("../nds7/io.zig");
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stat: nds7.Vramstat = .{ .raw = 0x00 },
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/// Write-Only (according to melonDS these are readable lol)
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cnt_a: nds9.Vramcnt.A = .{ .raw = 0x00 },
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cnt_b: nds9.Vramcnt.A = .{ .raw = 0x00 },
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cnt_c: nds9.Vramcnt.C = .{ .raw = 0x00 },
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cnt_d: nds9.Vramcnt.C = .{ .raw = 0x00 },
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cnt_e: nds9.Vramcnt.E = .{ .raw = 0x00 },
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cnt_f: nds9.Vramcnt.C = .{ .raw = 0x00 },
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cnt_g: nds9.Vramcnt.C = .{ .raw = 0x00 },
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cnt_h: nds9.Vramcnt.H = .{ .raw = 0x00 },
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cnt_i: nds9.Vramcnt.H = .{ .raw = 0x00 },
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};
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pub fn init(self: *@This(), allocator: Allocator) !void {
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const buf = try allocator.create([buf_len]u8);
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errdefer allocator.destroy(buf);
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@memset(buf, 0);
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const tables = try allocator.alloc(?[*]u8, 2 * table_len);
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@memset(tables, null);
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self.* = .{
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.nds9_table = tables[0..table_len],
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.nds7_table = tables[table_len .. 2 * table_len],
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._buf = buf,
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};
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// ROMS like redpanda.nds won't write to VRAMCNT before trying to write to VRAM
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// therefore we assume some default allocation (in this casee VRAMCNT_A -> VRAMCNT_I are 0x00)
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self.update();
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}
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pub fn deinit(self: @This(), allocator: Allocator) void {
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allocator.destroy(self._buf);
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const ptr: [*]?[*]const u8 = @ptrCast(@constCast(self.nds9_table));
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allocator.free(ptr[0 .. 2 * table_len]);
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}
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/// NDS7 VRAMSTAT
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pub fn stat(self: *const @This()) Io.Vramstat {
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const vram_c: u8 = @intFromBool(self.io.cnt_c.enable.read() and self.io.cnt_c.mst.read() == 2);
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const vram_d: u8 = @intFromBool(self.io.cnt_d.enable.read() and self.io.cnt_d.mst.read() == 2);
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return .{ .raw = (vram_d << 1) | vram_c };
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}
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const Kind = enum {
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a,
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b,
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c,
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d,
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e,
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f,
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g,
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h,
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i,
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/// In Bytes
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inline fn size(self: @This()) u32 {
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return switch (self) {
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.a => 128 * KiB,
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.b => 128 * KiB,
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.c => 128 * KiB,
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.d => 128 * KiB,
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.e => 64 * KiB,
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.f => 16 * KiB,
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.g => 16 * KiB,
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.h => 32 * KiB,
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.i => 16 * KiB,
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};
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}
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};
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// TODO: Rename
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fn range(comptime kind: Kind, mst: u3, offset: u2) u32 {
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const ofs: u32 = offset;
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// panic messages are from GBATEK
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return switch (kind) {
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.a => switch (mst) {
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0 => 0x0680_0000,
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1 => 0x0600_0000 + (0x0002_0000 * ofs),
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2 => 0x0640_0000 + (0x0002_0000 * (ofs & 0b01)),
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3 => @panic("VRAMCNT_A: Slot OFS(0-3)"),
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else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
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},
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.b => switch (mst) {
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0 => 0x0682_0000,
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1 => 0x0600_0000 + (0x0002_0000 * ofs),
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2 => 0x0640_0000 + (0x0002_0000 * (ofs & 0b01)),
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3 => @panic("VRAMCNT_B: Slot OFS(0-3)"),
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else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
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},
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.c => switch (mst) {
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0 => 0x0684_0000,
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1 => 0x0600_0000 + (0x0002_0000 * ofs),
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2 => 0x0600_0000 + (0x0002_0000 * (ofs & 0b01)),
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3 => @panic("VRAMCNT_C: Slot OFS(0-3)"),
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4 => 0x0620_0000,
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else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
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},
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.d => switch (mst) {
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0 => 0x0686_0000,
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1 => 0x0600_0000 + (0x0002_0000 * ofs),
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2 => 0x0600_0000 + (0x0002_0000 * (ofs & 0b01)),
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3 => @panic("VRAMCNT_D: Slot OFS(0-3)"),
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4 => 0x0660_0000,
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else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
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},
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.e => switch (mst) {
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0 => 0x0688_0000,
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1 => 0x0600_0000,
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2 => 0x0640_0000,
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3 => @panic("VRAMCNT_E: Slots 0-3"),
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else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
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},
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.f => switch (mst) {
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0 => 0x0689_0000,
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1 => 0x0600_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
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2 => 0x0640_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
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3 => @panic("VRAMCNT_F: Slot (OFS.0*1)+(OFS.1*4)"),
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4 => @panic("VRAMCNT_F: Slot 0-1 (OFS=0), Slot 2-3 (OFS=1)"),
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5 => @panic("VRAMCNT_F: Slot 0"),
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else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
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},
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.g => switch (mst) {
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0 => 0x0689_4000,
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1 => 0x0600_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
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2 => 0x0640_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
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3 => @panic("VRAMCNT_G: Slot (OFS.0*1)+(OFS.1*4)"),
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4 => @panic("VRAMCNT_G: Slot 0-1 (OFS=0), Slot 2-3 (OFS=1)"),
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5 => @panic("VRAMCNT_G: Slot 0"),
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else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
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},
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.h => switch (mst) {
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0 => 0x0689_8000,
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1 => 0x0620_0000,
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2 => @panic("VRAMCNT_H: Slot 0-3"),
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else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
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},
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.i => switch (mst) {
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0 => 0x068A_0000,
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1 => 0x0620_8000,
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2 => 0x0660_0000,
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3 => @panic("Slot 0"),
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else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
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},
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};
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}
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fn buf_offset(comptime kind: Kind) usize {
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// zig fmt: off
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return switch (kind) {
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.a => 0, // 0x00000
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.b => (128 * KiB) * 1, // 0x20000 (+ 0x20000)
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.c => (128 * KiB) * 2, // 0x40000 (+ 0x20000)
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.d => (128 * KiB) * 3, // 0x60000 (+ 0x20000)
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.e => (128 * KiB) * 4, // 0x80000 (+ 0x20000)
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.f => (128 * KiB) * 4 + (64 * KiB), // 0x90000 (+ 0x10000)
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.g => (128 * KiB) * 4 + (64 * KiB) + (16 * KiB) * 1, // 0x94000 (+ 0x04000)
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.h => (128 * KiB) * 4 + (64 * KiB) + (16 * KiB) * 2, // 0x98000 (+ 0x04000)
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.i => (128 * KiB) * 4 + (64 * KiB) + (16 * KiB) * 2 + (32 * KiB) // 0xA0000 (+ 0x08000)
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};
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// zig fmt: on
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}
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fn CntType(comptime kind: Kind) type {
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const Vramcnt = @import("../nds9/io.zig").Vramcnt;
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return switch (kind) {
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.a => Vramcnt.A,
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.b => Vramcnt.A,
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.c => Vramcnt.C,
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.d => Vramcnt.C,
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.e => Vramcnt.E,
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.f => Vramcnt.C,
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.g => Vramcnt.C,
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.h => Vramcnt.H,
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.i => Vramcnt.H,
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};
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}
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fn cntValue(self: *const @This(), comptime kind: Kind) CntType(kind) {
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return switch (kind) {
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.a => self.io.cnt_a,
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.b => self.io.cnt_b,
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.c => self.io.cnt_c,
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.d => self.io.cnt_d,
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.e => self.io.cnt_e,
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.f => self.io.cnt_f,
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.g => self.io.cnt_g,
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.h => self.io.cnt_h,
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.i => self.io.cnt_i,
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};
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}
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// TODO: We always update the entirety of VRAM when that argubably isn't necessary
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pub fn update(self: *@This()) void {
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const nds9_tbl = @constCast(self.nds9_table);
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const nds7_tbl = @constCast(self.nds7_table);
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for (nds9_tbl, nds7_tbl, 0..) |*nds9_ptr, *nds7_ptr, i| {
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const addr = 0x0600_0000 + (i * page_size);
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inline for (std.meta.fields(Kind)) |f| {
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const kind = @field(Kind, f.name);
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const cnt = cntValue(self, kind);
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const ofs = switch (kind) {
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.e, .h, .i => 0,
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else => cnt.offset.read(),
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};
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const min = range(kind, cnt.mst.read(), ofs);
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const max = min + kind.size();
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const offset = addr & (kind.size() - 1);
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if (min <= addr and addr < max) {
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if ((kind == .c or kind == .d) and cnt.mst.read() == 2) {
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// Allocate to ARM7
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nds7_ptr.* = self._buf[buf_offset(kind) + offset ..].ptr;
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} else {
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nds9_ptr.* = self._buf[buf_offset(kind) + offset ..].ptr;
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}
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}
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}
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}
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}
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// TODO: Rename
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const Device = enum { nds9, nds7 };
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pub fn read(self: @This(), comptime T: type, comptime dev: Device, address: u32) T {
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const masked_addr = address & (addr_space_size - 1);
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const page = masked_addr >> bits;
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const offset = masked_addr & (page_size - 1);
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const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
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if (table[page]) |some_ptr| {
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const ptr: [*]const T = @ptrCast(@alignCast(some_ptr));
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return ptr[offset / @sizeOf(T)];
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}
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log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped VRAM space", .{ @tagName(dev), T, address });
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return 0x00;
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}
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pub fn write(self: *@This(), comptime T: type, comptime dev: Device, address: u32, value: T) void {
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const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
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const masked_addr = address & (addr_space_size - 1);
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const page = masked_addr >> bits;
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const offset = masked_addr & (page_size - 1);
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const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
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if (table[page]) |some_ptr| {
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const ptr: [*]T = @ptrCast(@alignCast(some_ptr));
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ptr[offset / @sizeOf(T)] = value;
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return;
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}
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log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped VRA< space", .{ @tagName(dev), T, address, value });
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}
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91
src/core/ppu/engine.zig
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91
src/core/ppu/engine.zig
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@@ -0,0 +1,91 @@
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const std = @import("std");
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const Bus = @import("../nds9/Bus.zig");
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const FrameBuffer = @import("../ppu.zig").FrameBuffer;
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const DispcntA = @import("../nds9/io.zig").DispcntA;
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const DispcntB = @import("../nds9/io.zig").DispcntB;
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const Dispstat = @import("../nds9/io.zig").Dispstat;
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const Vcount = @import("../nds9/io.zig").Vcount;
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const PowCnt = @import("../nds9/io.zig").PowCnt;
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const width = @import("../ppu.zig").screen_width;
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const height = @import("../ppu.zig").screen_height;
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const EngineKind = enum { a, b };
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pub const EngineA = Engine(.a);
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pub const EngineB = Engine(.b);
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fn Engine(comptime kind: EngineKind) type {
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const log = std.log.scoped(.engine2d);
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_ = log; // TODO: specify between 2D-A and 2D-B
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// FIXME: don't commit zig crimes
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const Type = struct {
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fn inner(comptime TypeA: type, comptime TypeB: type) type {
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return if (kind == .a) TypeA else TypeB;
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}
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}.inner;
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return struct {
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dispcnt: Type(DispcntA, DispcntB) = .{ .raw = 0x0000_0000 },
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dispstat: Dispstat = .{ .raw = 0x0000_0000 },
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vcount: Vcount = .{ .raw = 0x0000_0000 },
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pub fn drawScanline(self: *@This(), bus: *Bus, fb: *FrameBuffer, powcnt: *PowCnt) void {
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const disp_mode = self.dispcnt.display_mode.read();
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switch (disp_mode) {
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0 => { // Display Off
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const buf = switch (kind) {
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.a => if (powcnt.display_swap.read()) fb.top(.back) else fb.btm(.back),
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.b => if (powcnt.display_swap.read()) fb.btm(.back) else fb.top(.back),
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};
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@memset(buf, 0xFF); // set everything to white
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},
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1 => @panic("TODO: standard graphics display (text mode, etc)"),
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2 => { // VRAM display
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if (kind == .b) return;
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// TODO: Master Brightness can still affect this mode
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const scanline: u32 = self.vcount.scanline.read();
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const buf = if (powcnt.display_swap.read()) fb.top(.back) else fb.btm(.back);
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const scanline_buf = blk: {
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const rgba_ptr: *[width * height]u32 = @ptrCast(@alignCast(buf));
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break :blk rgba_ptr[width * scanline ..][0..width];
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};
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const base_addr: u32 = 0x0680_0000 + (width * @sizeOf(u16)) * @as(u32, scanline);
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for (scanline_buf, 0..) |*rgba, i| {
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const addr = base_addr + @as(u32, @intCast(i)) * @sizeOf(u16);
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rgba.* = rgba888(bus.dbgRead(u16, addr));
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}
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},
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3 => {
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if (kind == .b) return;
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@panic("TODO: main memory display");
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},
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}
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}
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};
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}
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inline fn rgba888(bgr555: u16) u32 {
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const b: u32 = bgr555 >> 10 & 0x1F;
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const g: u32 = bgr555 >> 5 & 0x1F;
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const r: u32 = bgr555 & 0x1F;
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// zig fmt: off
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return (r << 3 | r >> 2) << 24
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| (g << 3 | g >> 2) << 16
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| (b << 3 | b >> 2) << 8
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| 0xFF;
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// zig fmt: on
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}
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