529 lines
13 KiB
Rust
529 lines
13 KiB
Rust
use crate::bus::{Bus, BusIo, BOOT_SIZE};
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use crate::instruction::Instruction;
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use crate::interrupt::{InterruptEnable, InterruptFlag};
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use crate::Cycle;
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use bitfield::bitfield;
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use std::fmt::{Display, Formatter, Result as FmtResult};
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#[derive(Debug, Default)]
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pub struct Cpu {
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pub bus: Bus,
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reg: Registers,
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flags: Flags,
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ime: ImeState,
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state: State,
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}
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impl Cpu {
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#[allow(dead_code)]
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pub(crate) fn without_boot() -> Self {
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Self {
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reg: Registers {
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a: 0x01,
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b: 0x00,
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c: 0x13,
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d: 0x00,
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e: 0xD8,
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h: 0x01,
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l: 0x4D,
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sp: 0xFFFE,
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pc: 0x0100,
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},
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flags: 0xb0.into(),
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..Default::default()
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}
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}
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pub(crate) fn with_boot(rom: [u8; BOOT_SIZE]) -> Self {
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Self {
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bus: Bus::with_boot(rom),
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..Default::default()
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}
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}
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pub(crate) fn ime(&self) -> ImeState {
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self.ime
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}
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pub(crate) fn set_ime(&mut self, state: ImeState) {
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self.ime = state;
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}
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pub(crate) fn halt_cpu(&mut self, kind: HaltKind) {
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self.state = State::Halt(kind);
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}
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fn resume_execution(&mut self) {
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self.state = State::Execute;
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}
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pub(crate) fn is_halted(&self) -> bool {
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matches!(self.state, State::Halt(_))
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}
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pub(crate) fn halt_kind(&self) -> Option<HaltKind> {
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match self.state {
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State::Halt(kind) => Some(kind),
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_ => None,
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}
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}
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}
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impl Cpu {
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/// Fetch an [Instruction] from the memory bus
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/// (4 cycles)
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fn fetch(&mut self) -> u8 {
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let byte = self.read_byte(self.reg.pc);
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self.bus.clock();
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self.reg.pc += 1;
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byte
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}
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/// Decode a byte into an [SM83](Cpu) [Instruction]
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///
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/// If opcode == 0xCB, then decoding costs 4 cycles.
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/// Otherwise, decoding is free
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pub(crate) fn decode(&mut self, opcode: u8) -> Instruction {
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if opcode == 0xCB {
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Instruction::decode(self.fetch(), true)
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} else {
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Instruction::decode(opcode, false)
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}
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}
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/// Execute an [Instruction].
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///
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/// The amount of cycles necessary to execute an instruction range from
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/// 0 to 20 T-cycles
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fn execute(&mut self, instruction: Instruction) -> Cycle {
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Instruction::execute(self, instruction)
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}
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/// Perform the [`Cpu::fetch()`] [`Cpu::decode()`] [`Cpu::execute()`]
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/// routine.
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///
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/// Handle HALT and interrupts.
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pub fn step(&mut self) -> Cycle {
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// Log instructions
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// if self.reg.pc > 0xFF {
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// let out = std::io::stdout();
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// let _ = self._print_logs(out.lock());
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// }
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if let Some(elapsed) = self.handle_interrupt() {
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return elapsed;
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}
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if let Some(kind) = self.halt_kind() {
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use HaltKind::*;
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self.bus.clock();
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let elapsed = match kind {
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ImeEnabled | NonePending => 4,
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SomePending => todo!("Implement HALT bug"),
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};
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return elapsed;
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}
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let opcode = self.fetch();
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let instr = self.decode(opcode);
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let elapsed = self.execute(instr);
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self.handle_ei();
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// For use in Blargg's Test ROMs
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if self.read_byte(0xFF02) == 0x81 {
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let c = self.read_byte(0xFF01) as char;
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self.write_byte(0xFF02, 0x00);
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eprint!("{}", c);
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}
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elapsed
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}
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}
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impl BusIo for Cpu {
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fn read_byte(&self, addr: u16) -> u8 {
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self.bus.read_byte(addr)
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}
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fn write_byte(&mut self, addr: u16, byte: u8) {
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self.bus.write_byte(addr, byte);
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}
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}
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impl Cpu {
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#[inline]
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pub(crate) fn bus(&self) -> &Bus {
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&self.bus
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}
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#[inline]
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pub(crate) fn bus_mut(&mut self) -> &mut Bus {
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&mut self.bus
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}
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fn handle_ei(&mut self) {
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match self.ime {
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ImeState::EiExecuted => self.ime = ImeState::Pending,
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ImeState::Pending => self.ime = ImeState::Enabled,
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ImeState::Disabled | ImeState::Enabled => {}
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}
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}
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pub(crate) fn int_request(&self) -> u8 {
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self.read_byte(0xFF0F)
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}
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pub(crate) fn int_enable(&self) -> u8 {
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self.read_byte(0xFFFF)
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}
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fn handle_interrupt(&mut self) -> Option<Cycle> {
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let irq = self.int_request();
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let enable = self.int_enable();
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// TODO: Ensure that this behaviour is correct
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if self.is_halted() {
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// When we're here either a HALT with IME set or
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// a HALT with IME not set and No pending Interrupts was called
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if irq & enable != 0 {
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// The if self.ime() below correctly follows the "resuming from HALT" behaviour so
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// nothing actually needs to be added here. This is just documentation
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// since it's a bit weird why nothing is being done
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self.resume_execution();
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}
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}
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match self.ime() {
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ImeState::Enabled => {
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let mut irq: InterruptFlag = irq.into();
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let enable: InterruptEnable = enable.into();
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let rst_vector = if irq.vblank() && enable.vblank() {
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// Handle VBlank Interrupt
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irq.set_vblank(false);
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// INT 40h
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Some(0x40)
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} else if irq.lcd_stat() && enable.lcd_stat() {
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// Handle LCD STAT Interrupt
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irq.set_lcd_stat(false);
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// INT 48h
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Some(0x48)
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} else if irq.timer() && enable.timer() {
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// Handle Timer Interrupt
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irq.set_timer(false);
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// INT 50h
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Some(0x50)
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} else if irq.serial() && enable.serial() {
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// Handle Serial Interrupt
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irq.set_serial(false);
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// INT 58h
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Some(0x58)
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} else if irq.joypad() && enable.joypad() {
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// Handle Joypad Interrupt
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irq.set_joypad(false);
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// INT 60h
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Some(0x60)
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} else {
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None
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};
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match rst_vector {
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Some(vector) => {
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// Write the Changes to 0xFF0F and 0xFFFF registers
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self.write_byte(0xFF0F, irq.into());
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// Disable all future interrupts
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self.set_ime(ImeState::Disabled);
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Some(Instruction::reset(self, vector))
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}
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None => None,
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}
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}
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_ => None,
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}
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}
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}
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#[derive(Debug, Clone, Copy)]
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enum State {
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Execute,
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Halt(HaltKind),
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// Stop,
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}
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impl Default for State {
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fn default() -> Self {
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Self::Execute
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}
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}
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impl Cpu {
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pub(crate) fn set_register(&mut self, register: Register, value: u8) {
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use Register::*;
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match register {
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A => self.reg.a = value,
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B => self.reg.b = value,
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C => self.reg.c = value,
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D => self.reg.d = value,
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E => self.reg.e = value,
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H => self.reg.h = value,
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L => self.reg.l = value,
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}
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}
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pub(crate) fn register(&self, register: Register) -> u8 {
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use Register::*;
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match register {
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A => self.reg.a,
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B => self.reg.b,
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C => self.reg.c,
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D => self.reg.d,
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E => self.reg.e,
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H => self.reg.h,
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L => self.reg.l,
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}
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}
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pub(crate) fn register_pair(&self, pair: RegisterPair) -> u16 {
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use RegisterPair::*;
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match pair {
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AF => (self.reg.a as u16) << 8 | u8::from(self.flags) as u16,
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BC => (self.reg.b as u16) << 8 | self.reg.c as u16,
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DE => (self.reg.d as u16) << 8 | self.reg.e as u16,
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HL => (self.reg.h as u16) << 8 | self.reg.l as u16,
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SP => self.reg.sp,
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PC => self.reg.pc,
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}
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}
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pub(crate) fn set_register_pair(&mut self, pair: RegisterPair, value: u16) {
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use RegisterPair::*;
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let high = (value >> 8) as u8;
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let low = value as u8;
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match pair {
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AF => {
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self.reg.a = high;
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self.flags = low.into();
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}
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BC => {
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self.reg.b = high;
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self.reg.c = low;
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}
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DE => {
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self.reg.d = high;
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self.reg.e = low;
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}
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HL => {
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self.reg.h = high;
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self.reg.l = low;
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}
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SP => self.reg.sp = value,
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PC => self.reg.pc = value,
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}
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}
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pub(crate) fn flags(&self) -> &Flags {
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&self.flags
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}
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pub(crate) fn update_flags(&mut self, z: bool, n: bool, h: bool, c: bool) {
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self.flags.set_z(z);
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self.flags.set_n(n);
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self.flags.set_h(h);
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self.flags.set_c(c);
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}
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pub(crate) fn set_flags(&mut self, flags: Flags) {
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self.flags = flags;
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}
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}
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impl Cpu {
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fn _print_debug(&self, mut w: impl std::io::Write) -> std::io::Result<()> {
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write!(w, "A: {:02X} ", self.reg.a)?;
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write!(w, "F: {:02X} ", u8::from(self.flags))?;
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write!(w, "B: {:02X} ", self.reg.b)?;
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write!(w, "C: {:02X} ", self.reg.c)?;
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write!(w, "D: {:02X} ", self.reg.d)?;
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write!(w, "E: {:02X} ", self.reg.e)?;
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write!(w, "H: {:02X} ", self.reg.h)?;
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write!(w, "L: {:02X} ", self.reg.l)?;
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write!(w, "SP: {:04X} ", self.reg.sp)?;
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write!(w, "PC: 00:{:04X} ", self.reg.pc)?;
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write!(w, "({:02X} ", self.read_byte(self.reg.pc))?;
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write!(w, "{:02X} ", self.read_byte(self.reg.pc + 1))?;
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write!(w, "{:02X} ", self.read_byte(self.reg.pc + 2))?;
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write!(w, "{:02X})", self.read_byte(self.reg.pc + 3))?;
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writeln!(w, "| {:?}", self._dbg_instr())?;
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w.flush()
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}
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fn _print_logs(&self, mut w: impl std::io::Write) -> std::io::Result<()> {
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write!(w, "A: {:02X} ", self.reg.a)?;
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write!(w, "F: {:02X} ", u8::from(self.flags))?;
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write!(w, "B: {:02X} ", self.reg.b)?;
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write!(w, "C: {:02X} ", self.reg.c)?;
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write!(w, "D: {:02X} ", self.reg.d)?;
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write!(w, "E: {:02X} ", self.reg.e)?;
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write!(w, "H: {:02X} ", self.reg.h)?;
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write!(w, "L: {:02X} ", self.reg.l)?;
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write!(w, "SP: {:04X} ", self.reg.sp)?;
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write!(w, "PC: 00:{:04X} ", self.reg.pc)?;
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write!(w, "({:02X} ", self.read_byte(self.reg.pc))?;
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write!(w, "{:02X} ", self.read_byte(self.reg.pc + 1))?;
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write!(w, "{:02X} ", self.read_byte(self.reg.pc + 2))?;
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writeln!(w, "{:02X})", self.read_byte(self.reg.pc + 3))?;
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w.flush()
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}
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fn _dbg_instr(&self) -> Instruction {
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let byte = self.read_byte(self.reg.pc);
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if byte == 0xCB {
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Instruction::decode(self.read_byte(self.reg.pc + 1), true)
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} else {
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Instruction::decode(byte, false)
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}
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}
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}
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#[derive(Debug, Clone, Copy)]
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pub(crate) enum Register {
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A,
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B,
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C,
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D,
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E,
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H,
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L,
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}
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#[derive(Debug, Clone, Copy)]
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pub(crate) enum RegisterPair {
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AF,
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BC,
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DE,
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HL,
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SP,
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PC,
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}
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#[derive(Debug, Default)]
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struct Registers {
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a: u8,
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b: u8,
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c: u8,
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d: u8,
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e: u8,
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h: u8,
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l: u8,
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sp: u16,
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pc: u16,
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}
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bitfield! {
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pub struct Flags(u8);
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impl Debug;
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pub z, set_z: 7; // Zero Flag
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pub n, set_n: 6; // Subtraction Flag
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pub h, set_h: 5; // Half Carry Flag
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pub c, set_c: 4; // Carry Flag
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}
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impl Flags {
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pub(crate) fn update(&mut self, z: bool, n: bool, h: bool, c: bool) {
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self.set_z(z);
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self.set_n(n);
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self.set_h(h);
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self.set_c(c);
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}
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}
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impl Copy for Flags {}
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impl Clone for Flags {
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fn clone(&self) -> Self {
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*self
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}
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}
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impl Default for Flags {
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fn default() -> Self {
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Self(0)
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}
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}
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impl Display for Flags {
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fn fmt(&self, f: &mut Formatter<'_>) -> FmtResult {
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if self.z() {
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f.write_str("Z")?;
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} else {
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f.write_str("_")?;
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}
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if self.n() {
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f.write_str("N")?;
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} else {
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f.write_str("_")?;
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}
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if self.h() {
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f.write_str("H")?;
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} else {
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f.write_str("_")?;
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}
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if self.c() {
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f.write_str("C")
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} else {
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f.write_str("_")
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}
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}
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}
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impl From<Flags> for u8 {
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fn from(flags: Flags) -> Self {
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flags.0 & 0xF0
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}
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}
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impl From<u8> for Flags {
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fn from(byte: u8) -> Self {
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Self(byte & 0xF0)
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}
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}
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#[derive(Debug, Clone, Copy)]
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pub(crate) enum HaltKind {
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ImeEnabled,
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NonePending,
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SomePending,
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}
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#[derive(Debug, Clone, Copy)]
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pub(crate) enum ImeState {
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Disabled,
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EiExecuted,
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Pending,
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Enabled,
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}
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impl Default for ImeState {
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fn default() -> Self {
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Self::Disabled
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}
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}
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