506 lines
12 KiB
Rust
506 lines
12 KiB
Rust
use crate::bus::{Bus, BusIo};
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use crate::instruction::{Cycle, Instruction};
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use crate::interrupt::{InterruptEnable, InterruptFlag};
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use crate::joypad::Joypad;
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use crate::ppu::Ppu;
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use crate::sound::SampleSender;
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use crate::timer::Timer;
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use bitfield::bitfield;
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use std::fmt::{Display, Formatter, Result as FmtResult};
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#[derive(Debug, Clone, Default)]
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pub struct Cpu {
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pub bus: Bus,
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reg: Registers,
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flags: Flags,
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ime: ImeState,
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// TODO: Merge halted and state properties
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halted: Option<HaltState>,
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state: State,
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}
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impl Cpu {
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pub fn new() -> Self {
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Self {
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reg: Registers {
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a: 0x01,
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b: 0x00,
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c: 0x13,
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d: 0x00,
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e: 0xD8,
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h: 0x01,
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l: 0x4D,
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sp: 0xFFFE,
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pc: 0x0100,
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},
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flags: 0xb0.into(),
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..Default::default()
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}
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}
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pub fn boot_new(path: &str) -> anyhow::Result<Self> {
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Ok(Self {
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bus: Bus::with_boot(path)?,
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..Default::default()
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})
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}
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pub fn set_audio_src(&mut self, sender: SampleSender) {
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self.bus.pass_audio_src(sender)
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}
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pub(crate) fn ime(&self) -> ImeState {
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self.ime
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}
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pub(crate) fn set_ime(&mut self, state: ImeState) {
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self.ime = state;
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}
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pub(crate) fn halt(&mut self, state: HaltState) {
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self.halted = Some(state);
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}
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fn resume(&mut self) {
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self.halted = None;
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}
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pub(crate) fn halted(&self) -> Option<HaltState> {
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self.halted
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}
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fn inc_pc(&mut self) {
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self.reg.pc += 1;
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}
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pub fn load_cartridge(&mut self, path: &str) -> std::io::Result<()> {
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self.bus.load_cartridge(path)
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}
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pub fn rom_title(&self) -> Option<&str> {
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self.bus.rom_title()
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}
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}
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impl Cpu {
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fn fetch(&self) -> u8 {
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self.bus.read_byte(self.reg.pc)
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}
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pub(crate) fn decode(&mut self, opcode: u8) -> Instruction {
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Instruction::from_byte(self, opcode)
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}
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fn execute(&mut self, instruction: Instruction) -> Cycle {
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Instruction::execute(self, instruction)
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}
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pub fn step(&mut self) -> Cycle {
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// if !self.bus.boot_enabled() {
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// let out = std::io::stdout();
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// let handle = out.lock();
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// self.log_state(handle).unwrap();
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// }
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let cycles = match self.halted() {
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Some(state) => {
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use HaltState::*;
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match state {
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ImeEnabled | NonePending => Cycle::new(4),
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SomePending => todo!("Implement HALT bug"),
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}
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}
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None => {
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let opcode = self.fetch();
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self.inc_pc();
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let instr = self.decode(opcode);
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let cycles = self.execute(instr);
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self.check_ime();
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cycles
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}
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};
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let pending: u32 = cycles.into();
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for _ in 0..pending {
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self.bus.clock();
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}
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self.handle_interrupts();
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cycles
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}
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}
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impl BusIo for Cpu {
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fn read_byte(&self, addr: u16) -> u8 {
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self.bus.read_byte(addr)
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}
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fn write_byte(&mut self, addr: u16, byte: u8) {
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self.bus.write_byte(addr, byte);
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}
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}
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impl Cpu {
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pub(crate) fn read_imm_byte(&mut self, addr: u16) -> u8 {
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self.inc_pc(); // NB: the addr read in the line below will be equal to PC - 1 after this function call
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self.bus.read_byte(addr)
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}
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pub(crate) fn read_imm_word(&mut self, addr: u16) -> u16 {
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self.inc_pc();
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self.inc_pc(); // NB: the addr read in the line below will be equal to PC - 2 after this function call
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self.bus.read_word(addr)
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}
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pub(crate) fn write_word(&mut self, addr: u16, word: u16) {
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self.bus.write_word(addr, word)
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}
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}
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impl Cpu {
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pub fn ppu(&mut self) -> &Ppu {
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&self.bus.ppu
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}
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pub(crate) fn joypad_mut(&mut self) -> &mut Joypad {
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&mut self.bus.joypad
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}
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pub(crate) fn timer(&self) -> &Timer {
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&self.bus.timer
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}
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fn check_ime(&mut self) {
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match self.ime {
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ImeState::Pending => {
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// This is within the context of the EI instruction, we need to not update EI until the end of the
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// next executed Instruction
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self.ime = ImeState::PendingEnd;
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}
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ImeState::PendingEnd => {
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// The Instruction after EI has now been executed, so we want to enable the IME flag here
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self.ime = ImeState::Enabled;
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}
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ImeState::Disabled | ImeState::Enabled => {} // Do Nothing
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}
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}
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fn handle_interrupts(&mut self) {
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let req = self.read_byte(0xFF0F);
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let enabled = self.read_byte(0xFFFF);
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if self.halted.is_some() {
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// When we're here either a HALT with IME set or
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// a HALT with IME not set and No pending Interrupts was called
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if req & enabled != 0 {
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// The if self.ime() below correctly follows the "resuming from HALT" behaviour so
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// nothing actually needs to be added here. This is just documentation
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// since it's a bit weird why nothing is being done
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self.resume()
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}
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}
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if let ImeState::Enabled = self.ime() {
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let mut req: InterruptFlag = req.into();
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let enabled: InterruptEnable = enabled.into();
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let vector = if req.vblank() && enabled.vblank() {
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// Handle VBlank Interrupt
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req.set_vblank(false);
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// INT 40h
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Some(0x40)
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} else if req.lcd_stat() && enabled.lcd_stat() {
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// Handle LCD STAT Interrupt
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req.set_lcd_stat(false);
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// INT 48h
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Some(0x48)
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} else if req.timer() && enabled.timer() {
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// Handle Timer Interrupt
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req.set_timer(false);
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// INT 50h
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Some(0x50)
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} else if req.serial() && enabled.serial() {
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// Handle Serial Interrupt
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req.set_serial(false);
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// INT 58h
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Some(0x58)
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} else if req.joypad() && enabled.joypad() {
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// Handle Joypad Interrupt
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req.set_joypad(false);
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// INT 60h
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Some(0x60)
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} else {
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None
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};
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let _ = match vector {
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Some(address) => {
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// Write the Changes to 0xFF0F and 0xFFFF registers
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self.write_byte(0xFF0F, req.into());
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// Disable all future interrupts
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self.set_ime(ImeState::Disabled);
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Instruction::reset(self, address)
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}
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None => Cycle::new(0), // NO Interrupts were enabled and / or requested
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};
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}
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}
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}
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#[derive(Debug, Copy, Clone)]
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enum State {
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Execute,
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// Halt,
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// Stop,
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}
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impl Default for State {
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fn default() -> Self {
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Self::Execute
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}
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}
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impl Cpu {
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pub(crate) fn set_register(&mut self, register: Register, value: u8) {
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use Register::*;
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match register {
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A => self.reg.a = value,
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B => self.reg.b = value,
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C => self.reg.c = value,
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D => self.reg.d = value,
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E => self.reg.e = value,
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H => self.reg.h = value,
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L => self.reg.l = value,
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Flag => self.flags = value.into(),
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}
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}
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pub(crate) fn register(&self, register: Register) -> u8 {
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use Register::*;
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match register {
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A => self.reg.a,
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B => self.reg.b,
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C => self.reg.c,
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D => self.reg.d,
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E => self.reg.e,
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H => self.reg.h,
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L => self.reg.l,
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Flag => self.flags.into(),
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}
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}
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pub(crate) fn register_pair(&self, pair: RegisterPair) -> u16 {
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use RegisterPair::*;
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match pair {
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AF => (self.reg.a as u16) << 8 | u8::from(self.flags) as u16,
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BC => (self.reg.b as u16) << 8 | self.reg.c as u16,
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DE => (self.reg.d as u16) << 8 | self.reg.e as u16,
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HL => (self.reg.h as u16) << 8 | self.reg.l as u16,
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SP => self.reg.sp,
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PC => self.reg.pc,
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}
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}
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pub(crate) fn set_register_pair(&mut self, pair: RegisterPair, value: u16) {
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use RegisterPair::*;
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let high = (value >> 8) as u8;
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let low = value as u8;
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match pair {
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AF => {
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self.reg.a = high;
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self.flags = low.into();
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}
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BC => {
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self.reg.b = high;
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self.reg.c = low;
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}
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DE => {
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self.reg.d = high;
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self.reg.e = low;
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}
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HL => {
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self.reg.h = high;
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self.reg.l = low;
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}
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SP => self.reg.sp = value,
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PC => self.reg.pc = value,
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}
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}
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pub(crate) fn flags(&self) -> &Flags {
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&self.flags
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}
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pub(crate) fn set_flags(&mut self, flags: Flags) {
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self.flags = flags;
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}
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}
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impl Cpu {
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fn _log_state(&self, mut writer: impl std::io::Write) -> std::io::Result<()> {
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write!(writer, "A: {:02X} ", self.reg.a)?;
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write!(writer, "F: {:02X} ", u8::from(self.flags))?;
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write!(writer, "B: {:02X} ", self.reg.b)?;
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write!(writer, "C: {:02X} ", self.reg.c)?;
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write!(writer, "D: {:02X} ", self.reg.d)?;
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write!(writer, "E: {:02X} ", self.reg.e)?;
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write!(writer, "H: {:02X} ", self.reg.h)?;
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write!(writer, "L: {:02X} ", self.reg.l)?;
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write!(writer, "SP: {:04X} ", self.reg.sp)?;
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write!(writer, "PC: 00:{:04X} ", self.reg.pc)?;
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write!(writer, "({:02X} ", self.read_byte(self.reg.pc))?;
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write!(writer, "{:02X} ", self.read_byte(self.reg.pc + 1))?;
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write!(writer, "{:02X} ", self.read_byte(self.reg.pc + 2))?;
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writeln!(writer, "{:02X})", self.read_byte(self.reg.pc + 3))?;
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writer.flush()?;
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Ok(())
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}
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}
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#[derive(Debug, Copy, Clone)]
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pub(crate) enum Register {
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A,
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B,
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C,
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D,
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E,
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H,
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L,
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Flag,
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}
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#[derive(Debug, Copy, Clone)]
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pub(crate) enum RegisterPair {
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AF,
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BC,
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DE,
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HL,
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SP,
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PC,
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}
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#[derive(Debug, Copy, Clone, Default)]
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struct Registers {
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a: u8,
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b: u8,
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c: u8,
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d: u8,
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e: u8,
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h: u8,
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l: u8,
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sp: u16,
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pc: u16,
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}
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bitfield! {
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pub struct Flags(u8);
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impl Debug;
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pub z, set_z: 7; // Zero Flag
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pub n, set_n: 6; // Subtraction Flag
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pub h, set_h: 5; // Half Carry Flag
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pub c, set_c: 4; // Carry Flag
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}
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impl Flags {
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pub(crate) fn update(&mut self, z: bool, n: bool, h: bool, c: bool) {
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self.set_z(z);
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self.set_n(n);
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self.set_h(h);
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self.set_c(c);
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}
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}
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impl Copy for Flags {}
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impl Clone for Flags {
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fn clone(&self) -> Self {
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*self
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}
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}
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impl Default for Flags {
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fn default() -> Self {
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Self(0)
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}
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}
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impl Display for Flags {
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fn fmt(&self, f: &mut Formatter<'_>) -> FmtResult {
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if self.z() {
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f.write_str("Z")?;
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} else {
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f.write_str("_")?;
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}
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if self.n() {
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f.write_str("N")?;
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} else {
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f.write_str("_")?;
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}
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if self.h() {
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f.write_str("H")?;
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} else {
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f.write_str("_")?;
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}
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if self.c() {
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f.write_str("C")
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} else {
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f.write_str("_")
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}
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}
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}
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impl From<Flags> for u8 {
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fn from(flags: Flags) -> Self {
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flags.0 & 0xF0
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}
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}
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impl From<u8> for Flags {
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fn from(byte: u8) -> Self {
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Self(byte & 0xF0)
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}
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}
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#[derive(Debug, Clone, Copy)]
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pub(crate) enum HaltState {
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ImeEnabled,
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NonePending,
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SomePending,
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}
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#[derive(Debug, Clone, Copy)]
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pub(crate) enum ImeState {
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Disabled,
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Pending,
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PendingEnd,
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Enabled,
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}
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impl Default for ImeState {
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fn default() -> Self {
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Self::Disabled
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}
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}
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