371 lines
14 KiB
Rust
371 lines
14 KiB
Rust
use super::cartridge::Cartridge;
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use super::high_ram::HighRam;
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use super::instruction::Cycle;
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use super::interrupt::{Interrupt, InterruptFlag};
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use super::joypad::Joypad;
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use super::ppu::Ppu;
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use super::serial::Serial;
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use super::sound::Sound;
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use super::timer::Timer;
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use super::work_ram::{VariableWorkRam, WorkRam};
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use std::{fs::File, io::Read};
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const BOOT_ROM_SIZE: usize = 0x100;
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#[derive(Debug, Clone)]
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pub struct Bus {
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boot: Option<[u8; BOOT_ROM_SIZE]>, // Boot ROM is 256b long
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cartridge: Option<Cartridge>,
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pub ppu: Ppu,
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work_ram: WorkRam,
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var_ram: VariableWorkRam,
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timer: Timer,
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int: Interrupt,
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sound: Sound,
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high_ram: HighRam,
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serial: Serial,
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pub joypad: Joypad,
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}
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impl Default for Bus {
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fn default() -> Self {
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Self {
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boot: None,
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cartridge: None,
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ppu: Default::default(),
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work_ram: Default::default(),
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var_ram: Default::default(),
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timer: Default::default(),
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int: Default::default(),
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sound: Default::default(),
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high_ram: Default::default(),
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serial: Default::default(),
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joypad: Default::default(),
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}
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}
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}
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impl Bus {
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pub fn with_boot(path: &str) -> anyhow::Result<Self> {
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let mut file = File::open(path)?;
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let mut boot_rom = [0u8; 256];
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file.read_exact(&mut boot_rom)?;
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Ok(Self {
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boot: Some(boot_rom),
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..Default::default()
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})
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}
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pub fn load_cartridge(&mut self, path: &str) -> std::io::Result<()> {
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self.cartridge = Some(Cartridge::new(path)?);
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Ok(())
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}
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pub fn rom_title(&self) -> Option<&str> {
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self.cartridge.as_ref()?.title()
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}
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pub fn step(&mut self, cycles: Cycle) {
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self.ppu.step(cycles);
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self.timer.step(cycles);
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self.sound.step(cycles);
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}
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pub fn timer(&self) -> Timer {
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self.timer
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}
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}
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impl Bus {
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pub fn read_byte(&self, addr: u16) -> u8 {
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match addr {
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0x0000..=0x3FFF => {
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// 16KB ROM bank 00
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if addr < 0x100 {
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if let Some(boot) = self.boot {
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return boot[addr as usize];
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}
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}
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match self.cartridge.as_ref() {
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Some(cart) => cart.read_byte(addr),
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None => panic!("Tried to read from a non-existent cartridge"),
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}
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}
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0x4000..=0x7FFF => match self.cartridge.as_ref() {
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// 16KB ROM Bank 01 -> NN (switchable via MB)
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Some(cart) => cart.read_byte(addr),
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None => panic!("Tried to read from a non-existent cartridge"),
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},
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0x8000..=0x9FFF => {
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// 8KB Video RAM
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self.ppu.read_byte(addr)
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}
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0xA000..=0xBFFF => match self.cartridge.as_ref() {
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// 8KB External RAM
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Some(cart) => cart.read_byte(addr),
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None => panic!("Tried to read from a non-existent cartridge"),
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},
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0xC000..=0xCFFF => {
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// 4KB Work RAM Bank 0
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self.work_ram.read_byte(addr)
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}
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0xD000..=0xDFFF => {
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// 4KB Work RAM Bank 1 -> N
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self.var_ram.read_byte(addr)
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}
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0xE000..=0xFDFF => {
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// Mirror of 0xC000 to 0xDDFF (ECHO RAM)
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match addr & 0x1FFF {
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// 0xE000 ..= 0xEFFF
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0x0000..=0x0FFF => {
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// 4KB Work RAM Bank 0
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self.work_ram.read_byte(addr)
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}
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// 0xF000 ..= 0xFDFF
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0x1000..=0x1DFF => {
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// 4KB Work RAM Bank 1 -> N
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self.var_ram.read_byte(addr)
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}
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_ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
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}
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}
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0xFE00..=0xFE9F => {
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// Sprite Attribute Table
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self.ppu.oam.read_byte(addr)
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}
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0xFEA0..=0xFEFF => {
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// eprintln!("Read from {:#06X}, which is prohibited", addr);
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// TODO: Properly Emulate what can happen here
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0x00
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}
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0xFF00..=0xFF7F => {
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// IO Registers
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// Every address here starts with 0xFF so we can just check the
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// low byte to figure out which register it is
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match addr & 0x00FF {
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0x00 => self.joypad.status.into(),
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0x01 => self.serial.next,
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0x02 => self.serial.control.into(),
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0x04 => (self.timer.divider >> 8) as u8,
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0x05 => self.timer.counter,
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0x06 => self.timer.modulo,
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0x07 => self.timer.control.into(),
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0x0F => self.interrupt_flag().into(),
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0x11 => self.sound.ch1.sound_duty.into(),
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0x12 => self.sound.ch1.vol_envelope.into(),
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0x14 => self.sound.ch1.freq_hi.into(),
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0x24 => self.sound.control.channel.into(),
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0x25 => self.sound.control.output.into(),
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0x26 => self.sound.control.status.into(),
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0x40 => self.ppu.control.into(),
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0x41 => self.ppu.stat.into(),
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0x42 => self.ppu.pos.scroll_y,
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0x43 => self.ppu.pos.scroll_x,
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0x44 => self.ppu.pos.line_y,
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0x45 => self.ppu.pos.ly_compare as u8,
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0x47 => self.ppu.monochrome.bg_palette.into(),
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0x48 => self.ppu.monochrome.obj_palette_0.into(),
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0x49 => self.ppu.monochrome.obj_palette_1.into(),
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0x4A => self.ppu.pos.window_y,
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0x4B => self.ppu.pos.window_x,
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0x4D => 0x00, // Reading from this address is useful on the CGB only
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_ => unimplemented!("Unable to read {:#06X} in I/O Registers", addr),
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}
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}
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0xFF80..=0xFFFE => {
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// High RAM
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self.high_ram.read_byte(addr)
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}
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0xFFFF => {
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// Interrupts Enable Register
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self.int.enable.into()
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}
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}
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}
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pub fn write_byte(&mut self, addr: u16, byte: u8) {
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match addr {
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0x0000..=0x3FFF => {
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// 16KB ROM bank 00
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match self.cartridge.as_mut() {
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Some(cart) => cart.write_byte(addr, byte),
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None => panic!("Tried to write into non-existent cartridge"),
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}
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}
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0x4000..=0x7FFF => {
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// 16KB ROM Bank 01 -> NN (switchable via MB)
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match self.cartridge.as_mut() {
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Some(cart) => cart.write_byte(addr, byte),
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None => panic!("Tried to write into non-existent cartridge"),
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}
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}
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0x8000..=0x9FFF => {
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// 8KB Video RAM
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self.ppu.write_byte(addr, byte);
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}
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0xA000..=0xBFFF => {
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// 8KB External RAM
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match self.cartridge.as_mut() {
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Some(cart) => cart.write_byte(addr, byte),
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None => panic!("Tried to write into non-existent cartridge"),
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}
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}
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0xC000..=0xCFFF => {
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// 4KB Work RAM Bank 0
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self.work_ram.write_byte(addr, byte);
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}
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0xD000..=0xDFFF => {
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// 4KB Work RAM Bank 1 -> N
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self.var_ram.write_byte(addr, byte);
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}
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0xE000..=0xFDFF => {
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// Mirror of 0xC000 to 0xDDFF (ECHO RAM)
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match addr & 0x1FFF {
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// 0xE000 ..= 0xEFFF
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0x0000..=0x0FFF => {
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// 4KB Work RAM Bank 0
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self.work_ram.write_byte(addr, byte);
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}
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// 0xF000 ..= 0xFDFF
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0x1000..=0x1DFF => {
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// 4KB Work RAM Bank 1 -> N
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self.var_ram.write_byte(addr, byte);
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}
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_ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
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}
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}
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0xFE00..=0xFE9F => {
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// Sprite Attribute Table
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self.ppu.oam.write_byte(addr, byte);
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}
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0xFEA0..=0xFEFF => {
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// eprintln!("Wrote {:#04X} to {:#06X}, which is prohibited", byte, addr);
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// TODO: Properly emulate what can happen here
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}
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0xFF00..=0xFF7F => {
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// IO Registers
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// Every address here starts with 0xFF so we can just check the
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// low byte to figure out which register it is
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match addr & 0x00FF {
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0x00 => self.joypad.status.update(byte),
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0x01 => self.serial.next = byte,
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0x02 => self.serial.control = byte.into(),
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0x04 => self.timer.divider = 0x0000,
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0x05 => self.timer.counter = byte,
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0x06 => self.timer.modulo = byte,
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0x07 => self.timer.control = byte.into(),
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0x0F => self.set_interrupt_flag(byte),
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0x11 => self.sound.ch1.sound_duty = byte.into(),
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0x12 => self.sound.ch1.vol_envelope = byte.into(),
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0x13 => self.sound.ch1.freq_lo = byte.into(),
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0x14 => self.sound.ch1.freq_hi = byte.into(),
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0x24 => self.sound.control.channel = byte.into(),
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0x25 => self.sound.control.output = byte.into(),
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0x26 => self.sound.control.status = byte.into(), // FIXME: Should we control which bytes are written to here?
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0x40 => self.ppu.control = byte.into(),
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0x41 => self.ppu.stat.update(byte),
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0x42 => self.ppu.pos.scroll_y = byte,
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0x43 => self.ppu.pos.scroll_x = byte,
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0x44 => self.ppu.pos.line_y = byte,
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0x45 => {
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// Update LYC
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self.ppu.pos.ly_compare = byte;
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// Update Coincidence Flag
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let are_equal = self.ppu.pos.line_y == byte;
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self.ppu.stat.set_coincidence(are_equal);
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// If enabled, request a LCD STAT interrupt
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if self.ppu.stat.coincidence_int() && are_equal {
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self.ppu.int.set_lcd_stat(true);
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}
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}
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0x47 => self.ppu.monochrome.bg_palette = byte.into(),
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0x48 => self.ppu.monochrome.obj_palette_0 = byte.into(),
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0x49 => self.ppu.monochrome.obj_palette_1 = byte.into(),
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0x4A => self.ppu.pos.window_y = byte,
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0x4B => self.ppu.pos.window_x = byte,
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0x4D => {} // Writing to this address is useful on the CGB only
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0x50 => {
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// Disable Boot ROM
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if byte != 0 {
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self.boot = None;
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}
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}
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_ => unimplemented!("Unable to write to {:#06X} in I/O Registers", addr),
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};
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}
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0xFF80..=0xFFFE => {
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// High RAM
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self.high_ram.write_byte(addr, byte);
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}
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0xFFFF => {
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// Interrupts Enable Register
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self.int.enable = byte.into();
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}
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}
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}
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pub fn read_word(&self, addr: u16) -> u16 {
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(self.read_byte(addr + 1) as u16) << 8 | self.read_byte(addr) as u16
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}
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pub fn write_word(&mut self, addr: u16, word: u16) {
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self.write_byte(addr + 1, (word >> 8) as u8);
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self.write_byte(addr, (word & 0x00FF) as u8);
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}
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}
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impl Bus {
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fn interrupt_flag(&self) -> InterruptFlag {
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// Read the current interrupt information from the PPU
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let vblank = self.ppu.int.vblank();
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let lcd_stat = self.ppu.int.lcd_stat();
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// Read the current interrupt information from the Joypad
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let joypad = self.joypad.interrupt();
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// Read the current interrupt information from the Timer
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let timer = self.timer.interrupt();
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// Copy the Interrupt Flag register 0xFF0F
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let mut flag = self.int.flag;
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// Update the flag to have the most accurate information
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flag.set_vblank(vblank);
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flag.set_lcd_stat(lcd_stat);
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flag.set_joypad(joypad);
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flag.set_timer(timer);
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flag
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}
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fn set_interrupt_flag(&mut self, byte: u8) {
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// Update the Interrupt register 0xFF0F
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self.int.flag = byte.into();
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let vblank = self.int.flag.vblank();
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let lcd_stat = self.int.flag.lcd_stat();
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let joypad = self.int.flag.joypad();
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let timer = self.int.flag.timer();
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// Update the PPU's instance of the following interrupts
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self.ppu.int.set_vblank(vblank);
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self.ppu.int.set_lcd_stat(lcd_stat);
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// Update the Joypad's instance of the following interrupts
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self.joypad.set_interrupt(joypad);
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// Update the Timer's instance of the following interrupts
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self.timer.set_interrupt(timer);
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}
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pub fn boot_enabled(&self) -> bool {
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self.boot.is_some()
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}
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}
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