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c7e3cb5b35
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9e36e86c14
86
src/apu.rs
86
src/apu.rs
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@ -1,4 +1,3 @@
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use crate::bus::BusIo;
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use crate::emu::SM83_CLOCK_SPEED;
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use crate::emu::SM83_CLOCK_SPEED;
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use gen::{AudioBuffer, AudioSender};
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use gen::{AudioBuffer, AudioSender};
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use types::ch1::{Sweep, SweepDirection};
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use types::ch1::{Sweep, SweepDirection};
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@ -19,15 +18,15 @@ const SAMPLE_INCREMENT: u64 = SAMPLE_RATE as u64;
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#[derive(Default, Debug, Clone)]
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#[derive(Default, Debug, Clone)]
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pub struct Apu {
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pub struct Apu {
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ctrl: SoundControl,
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pub(crate) ctrl: SoundControl,
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/// Tone & Sweep
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/// Tone & Sweep
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ch1: Channel1,
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pub(crate) ch1: Channel1,
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/// Tone
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/// Tone
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ch2: Channel2,
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pub(crate) ch2: Channel2,
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/// Wave
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/// Wave
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ch3: Channel3,
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pub(crate) ch3: Channel3,
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/// Noise
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/// Noise
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ch4: Channel4,
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pub(crate) ch4: Channel4,
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// Frame Sequencer
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// Frame Sequencer
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frame_seq_state: FrameSequencerState,
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frame_seq_state: FrameSequencerState,
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@ -39,66 +38,6 @@ pub struct Apu {
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buffer: AudioBuffer<(f32, f32)>,
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buffer: AudioBuffer<(f32, f32)>,
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}
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}
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impl BusIo for Apu {
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fn read_byte(&self, addr: u16) -> u8 {
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match addr & 0x00FF {
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0x11 => self.ch1.duty(),
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0x12 => self.ch1.envelope(),
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0x14 => self.ch1.freq_hi(),
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0x16 => self.ch2.duty(),
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0x17 => self.ch2.envelope(),
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0x19 => self.ch2.freq_hi(),
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0x1A => self.ch3.enabled(),
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0x1B => self.ch3.len(),
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0x1C => self.ch3.volume(),
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0x1E => self.ch3.freq_hi(),
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0x20 => self.ch4.len(),
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0x21 => self.ch4.envelope(),
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0x22 => self.ch4.poly(),
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0x23 => self.ch4.frequency(),
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0x24 => self.ctrl.channel(),
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0x25 => self.ctrl.output(),
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0x26 => self.ctrl.status(self),
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0x30..=0x3F => self.ch3.read_byte(addr),
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_ => {
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eprintln!("Read 0xFF from unused IO register {:#06X} [APU]", addr);
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0xFF
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}
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}
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}
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fn write_byte(&mut self, addr: u16, byte: u8) {
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match addr & 0x00FF {
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0x10 => self.ch1.set_sweep(byte),
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0x11 => self.ch1.set_duty(byte),
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0x12 => self.ch1.set_envelope(byte),
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0x13 => self.ch1.set_freq_lo(byte),
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0x14 => self.ch1.set_freq_hi(byte),
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0x16 => self.ch2.set_duty(byte),
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0x17 => self.ch2.set_envelope(byte),
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0x18 => self.ch2.set_freq_lo(byte),
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0x19 => self.ch2.set_freq_hi(byte),
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0x1A => self.ch3.set_enabled(byte),
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0x1B => self.ch3.set_len(byte),
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0x1C => self.ch3.set_volume(byte),
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0x1D => self.ch3.set_freq_lo(byte),
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0x1E => self.ch3.set_freq_hi(byte),
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0x20 => self.ch4.set_len(byte),
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0x21 => self.ch4.set_envelope(byte),
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0x22 => self.ch4.set_poly(byte),
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0x23 => self.ch4.set_freq_data(byte),
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0x24 => self.ctrl.set_channel(byte),
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0x25 => self.ctrl.set_output(byte),
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0x26 => self.set_status(byte),
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0x30..=0x3F => self.ch3.write_byte(addr, byte),
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_ => eprintln!(
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"Wrote {:#04X} to unused IO register {:#06X} [APU]",
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byte, addr
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),
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}
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}
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}
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impl Apu {
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impl Apu {
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pub(crate) fn clock(&mut self, div: u16) {
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pub(crate) fn clock(&mut self, div: u16) {
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use FrameSequencerState::*;
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use FrameSequencerState::*;
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@ -672,8 +611,7 @@ pub(crate) struct Channel3 {
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freq_lo: u8,
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freq_lo: u8,
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/// 0xFF1E | NR34 - Channel 3 Frequency high
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/// 0xFF1E | NR34 - Channel 3 Frequency high
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freq_hi: FrequencyHigh,
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freq_hi: FrequencyHigh,
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pub(crate) wave_ram: [u8; WAVE_PATTERN_RAM_LEN],
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wave_ram: [u8; WAVE_PATTERN_RAM_LEN],
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// Length Functionality
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// Length Functionality
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length_timer: u16,
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length_timer: u16,
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@ -682,19 +620,7 @@ pub(crate) struct Channel3 {
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offset: u8,
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offset: u8,
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}
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}
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impl BusIo for Channel3 {
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fn read_byte(&self, addr: u16) -> u8 {
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self.wave_ram[(addr - Self::WAVE_RAM_START_ADDR) as usize]
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}
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fn write_byte(&mut self, addr: u16, byte: u8) {
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self.wave_ram[(addr - Self::WAVE_RAM_START_ADDR) as usize] = byte;
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}
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}
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impl Channel3 {
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impl Channel3 {
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const WAVE_RAM_START_ADDR: u16 = 0xFF30;
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/// 0xFF1A | NR30 - Channel 3 Sound on/off
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/// 0xFF1A | NR30 - Channel 3 Sound on/off
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pub(crate) fn enabled(&self) -> u8 {
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pub(crate) fn enabled(&self) -> u8 {
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((self.enabled as u8) << 7) | 0x7F
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((self.enabled as u8) << 7) | 0x7F
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45
src/bus.rs
45
src/bus.rs
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@ -224,7 +224,25 @@ impl BusIo for Bus {
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0x06 => self.timer.modulo,
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0x06 => self.timer.modulo,
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0x07 => self.timer.ctrl.into(),
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0x07 => self.timer.ctrl.into(),
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0x0F => self.interrupt_flag().into(),
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0x0F => self.interrupt_flag().into(),
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0x10..=0x3F => self.apu.read_byte(addr),
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0x10 => self.apu.ch1.sweep(),
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0x11 => self.apu.ch1.duty(),
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0x12 => self.apu.ch1.envelope(),
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0x14 => self.apu.ch1.freq_hi(),
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0x16 => self.apu.ch2.duty(),
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0x17 => self.apu.ch2.envelope(),
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0x19 => self.apu.ch2.freq_hi(),
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0x1A => self.apu.ch3.enabled(),
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0x1B => self.apu.ch3.len(),
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0x1C => self.apu.ch3.volume(),
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0x1E => self.apu.ch3.freq_hi(),
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0x20 => self.apu.ch4.len(),
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0x21 => self.apu.ch4.envelope(),
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0x22 => self.apu.ch4.poly(),
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0x23 => self.apu.ch4.frequency(),
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0x24 => self.apu.ctrl.channel(),
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0x25 => self.apu.ctrl.output(),
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0x26 => self.apu.ctrl.status(&self.apu),
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0x30..=0x3F => self.apu.ch3.wave_ram[addr as usize - 0xFF30],
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0x40 => self.ppu.ctrl.into(),
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0x40 => self.ppu.ctrl.into(),
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0x41 => self.ppu.stat.into(),
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0x41 => self.ppu.stat.into(),
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0x42 => self.ppu.pos.scroll_y,
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0x42 => self.ppu.pos.scroll_y,
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@ -237,7 +255,7 @@ impl BusIo for Bus {
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0x49 => self.ppu.monochrome.obj_palette_1.into(),
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0x49 => self.ppu.monochrome.obj_palette_1.into(),
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0x4A => self.ppu.pos.window_y,
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0x4A => self.ppu.pos.window_y,
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0x4B => self.ppu.pos.window_x,
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0x4B => self.ppu.pos.window_x,
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0x4D => 0xFF, // TODO: CGB Specific Register
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0x4D => 0xFF, // CGB Specific Register
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_ => {
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_ => {
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eprintln!("Read 0xFF from unused IO register {:#06X}.", addr);
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eprintln!("Read 0xFF from unused IO register {:#06X}.", addr);
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0xFF
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0xFF
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@ -324,7 +342,28 @@ impl BusIo for Bus {
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0x06 => self.timer.modulo = byte,
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0x06 => self.timer.modulo = byte,
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0x07 => self.timer.ctrl = byte.into(),
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0x07 => self.timer.ctrl = byte.into(),
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0x0F => self.set_interrupt_flag(byte),
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0x0F => self.set_interrupt_flag(byte),
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0x10..=0x3F => self.apu.write_byte(addr, byte),
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0x10 => self.apu.ch1.set_sweep(byte),
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0x11 => self.apu.ch1.set_duty(byte),
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0x12 => self.apu.ch1.set_envelope(byte),
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0x13 => self.apu.ch1.set_freq_lo(byte),
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0x14 => self.apu.ch1.set_freq_hi(byte),
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0x16 => self.apu.ch2.set_duty(byte),
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0x17 => self.apu.ch2.set_envelope(byte),
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0x18 => self.apu.ch2.set_freq_lo(byte),
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0x19 => self.apu.ch2.set_freq_hi(byte),
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0x1A => self.apu.ch3.set_enabled(byte),
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0x1B => self.apu.ch3.set_len(byte),
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0x1C => self.apu.ch3.set_volume(byte),
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0x1D => self.apu.ch3.set_freq_lo(byte),
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0x1E => self.apu.ch3.set_freq_hi(byte),
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0x20 => self.apu.ch4.set_len(byte),
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0x21 => self.apu.ch4.set_envelope(byte),
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0x22 => self.apu.ch4.set_poly(byte),
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0x23 => self.apu.ch4.set_freq_data(byte),
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0x24 => self.apu.ctrl.set_channel(byte),
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0x25 => self.apu.ctrl.set_output(byte),
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0x26 => self.apu.set_status(byte),
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0x30..=0x3F => self.apu.ch3.wave_ram[addr as usize - 0xFF30] = byte,
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0x40 => self.ppu.ctrl = byte.into(),
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0x40 => self.ppu.ctrl = byte.into(),
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0x41 => self.ppu.stat.update(byte),
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0x41 => self.ppu.stat.update(byte),
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0x42 => self.ppu.pos.scroll_y = byte,
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0x42 => self.ppu.pos.scroll_y = byte,
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