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No commits in common. "c4226e6e767fb711ded4e0f70a5d73731db01019" and "865c11d53c76114b3587f11ff073a2c57543a2b6" have entirely different histories.
c4226e6e76
...
865c11d53c
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@ -4,6 +4,5 @@
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"tamasfe.even-better-toml",
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"serayuzgur.crates",
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"vadimcn.vscode-lldb",
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"donaldhays.rgbds-z80"
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]
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}
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27
src/cpu.rs
27
src/cpu.rs
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@ -73,15 +73,12 @@ impl Cpu {
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///
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/// If opcode == 0xCB, then decoding costs 4 cycles.
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/// Otherwise, decoding is free
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pub(crate) fn decode(&mut self, mut opcode: u8) -> Instruction {
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let instr = if opcode == 0xCB {
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opcode = self.fetch();
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Instruction::decode(opcode, true)
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pub(crate) fn decode(&mut self, opcode: u8) -> Instruction {
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if opcode == 0xCB {
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Instruction::decode(self.fetch(), true)
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} else {
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Instruction::decode(opcode, false)
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};
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instr.unwrap_or_else(|| panic!("{:#04X} is an invalid instruction", opcode))
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}
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}
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/// Execute an [Instruction].
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@ -366,15 +363,12 @@ impl Cpu {
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}
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fn _dbg_instr(&self) -> Instruction {
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let mut byte = self.read_byte(self.reg.pc);
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let instr = if byte == 0xCB {
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byte = self.read_byte(self.reg.pc + 1);
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Instruction::decode(byte, true)
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let byte = self.read_byte(self.reg.pc);
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if byte == 0xCB {
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Instruction::decode(self.read_byte(self.reg.pc + 1), true)
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} else {
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Instruction::decode(byte, false)
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};
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instr.unwrap_or_else(|| panic!("{:#04X} is an invalid instruction", byte))
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}
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}
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}
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@ -524,6 +518,9 @@ pub(crate) mod dbg {
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}
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pub(crate) fn ime(cpu: &Cpu) -> bool {
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matches!(cpu.ime, ImeState::Enabled)
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match cpu.ime {
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ImeState::Enabled => true,
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_ => false,
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}
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}
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}
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@ -1,6 +1,6 @@
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use self::add::{Source as AddSource, Target as AddTarget};
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use self::alu::Source as AluSource;
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use self::jump::{JpCond, JpLoc};
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use self::jump::{JumpCondition, JumpLocation};
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use self::load::{Source as LDSource, Target as LDTarget};
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use self::table::{
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alu_imm_instr, alu_reg_instr, flag_instr, group1, group2, group3, jump_cond, prefix_alu,
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@ -16,7 +16,7 @@ use crate::Cycle;
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pub(crate) enum Instruction {
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NOP,
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STOP,
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JR(JpCond),
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JR(JumpCondition),
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LD(LDTarget, LDSource),
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ADD(AddTarget, AddSource),
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LDHL,
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@ -38,13 +38,13 @@ pub(crate) enum Instruction {
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XOR(AluSource),
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OR(AluSource),
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CP(AluSource),
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RET(JpCond),
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RET(JumpCondition),
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POP(Group3RegisterPair),
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RETI,
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JP(JpCond, JpLoc),
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JP(JumpCondition, JumpLocation),
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DI,
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EI,
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CALL(JpCond),
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CALL(JumpCondition),
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PUSH(Group3RegisterPair),
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RST(u8),
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RLC(Register),
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@ -293,7 +293,7 @@ impl Instruction {
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let addr = pc.wrapping_add(byte as u16);
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match cond {
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JpCond::NotZero => {
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JumpCondition::NotZero => {
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if !flags.z() {
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Self::jump(cpu, addr);
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12
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@ -301,7 +301,7 @@ impl Instruction {
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8
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}
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}
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JpCond::Zero => {
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JumpCondition::Zero => {
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if flags.z() {
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Self::jump(cpu, addr);
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12
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@ -309,7 +309,7 @@ impl Instruction {
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8
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}
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}
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JpCond::NotCarry => {
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JumpCondition::NotCarry => {
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if !flags.c() {
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Self::jump(cpu, addr);
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12
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@ -317,7 +317,7 @@ impl Instruction {
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8
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}
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}
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JpCond::Carry => {
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JumpCondition::Carry => {
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if flags.c() {
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Self::jump(cpu, addr);
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12
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@ -325,7 +325,7 @@ impl Instruction {
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8
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}
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}
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JpCond::Always => {
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JumpCondition::Always => {
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Self::jump(cpu, addr);
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12
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}
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@ -837,7 +837,7 @@ impl Instruction {
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let flags: Flags = *cpu.flags();
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match cond {
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JpCond::NotZero => {
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JumpCondition::NotZero => {
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cpu.bus.clock(); // internal branch decision
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if !flags.z() {
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@ -848,7 +848,7 @@ impl Instruction {
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8
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}
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}
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JpCond::Zero => {
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JumpCondition::Zero => {
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cpu.bus.clock(); // internal branch decision
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if flags.z() {
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@ -859,7 +859,7 @@ impl Instruction {
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8
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}
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}
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JpCond::NotCarry => {
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JumpCondition::NotCarry => {
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cpu.bus.clock(); // internal branch decision
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if !flags.c() {
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@ -870,7 +870,7 @@ impl Instruction {
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8
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}
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}
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JpCond::Carry => {
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JumpCondition::Carry => {
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cpu.bus.clock(); // internal branch decision
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if flags.c() {
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@ -881,7 +881,7 @@ impl Instruction {
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8
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}
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}
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JpCond::Always => {
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JumpCondition::Always => {
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let addr = Self::pop(cpu);
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Self::jump(cpu, addr);
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16
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@ -908,13 +908,13 @@ impl Instruction {
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16
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}
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Instruction::JP(cond, location) => match location {
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JpLoc::HL => {
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JumpLocation::HL => {
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// JP HL | Store HL in program counter
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let right = cpu.register_pair(RegisterPair::HL);
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cpu.set_register_pair(RegisterPair::PC, right);
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4
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}
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JpLoc::ImmediateWord => {
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JumpLocation::ImmediateWord => {
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// JP cond u16 | Store u16 in program counter if condition is true
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// JP u16 | Store u16 in program counter
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let flags: Flags = *cpu.flags();
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@ -922,7 +922,7 @@ impl Instruction {
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let addr = Self::imm_word(cpu);
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match cond {
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JpCond::NotZero => {
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JumpCondition::NotZero => {
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if !flags.z() {
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Self::jump(cpu, addr);
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16
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@ -930,7 +930,7 @@ impl Instruction {
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12
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}
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}
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JpCond::Zero => {
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JumpCondition::Zero => {
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if flags.z() {
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Self::jump(cpu, addr);
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16
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@ -938,7 +938,7 @@ impl Instruction {
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12
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}
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}
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JpCond::NotCarry => {
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JumpCondition::NotCarry => {
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if !flags.c() {
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Self::jump(cpu, addr);
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16
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@ -946,7 +946,7 @@ impl Instruction {
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12
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}
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}
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JpCond::Carry => {
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JumpCondition::Carry => {
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if flags.c() {
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Self::jump(cpu, addr);
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16
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@ -954,7 +954,7 @@ impl Instruction {
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12
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}
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}
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JpCond::Always => {
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JumpCondition::Always => {
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Self::jump(cpu, addr);
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16
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}
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@ -980,7 +980,7 @@ impl Instruction {
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let return_addr = cpu.register_pair(RegisterPair::PC);
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match cond {
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JpCond::NotZero => {
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JumpCondition::NotZero => {
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if !flags.z() {
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cpu.bus.clock(); // internal branch decision
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Self::push(cpu, return_addr);
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@ -990,7 +990,7 @@ impl Instruction {
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12
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}
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}
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JpCond::Zero => {
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JumpCondition::Zero => {
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if flags.z() {
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cpu.bus.clock(); // internal branch decision
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Self::push(cpu, return_addr);
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@ -1000,7 +1000,7 @@ impl Instruction {
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12
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}
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}
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JpCond::NotCarry => {
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JumpCondition::NotCarry => {
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if !flags.c() {
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cpu.bus.clock(); // internal branch decision
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Self::push(cpu, return_addr);
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@ -1010,7 +1010,7 @@ impl Instruction {
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12
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}
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}
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JpCond::Carry => {
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JumpCondition::Carry => {
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if flags.c() {
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cpu.bus.clock(); // internal branch decision
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Self::push(cpu, return_addr);
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@ -1020,7 +1020,7 @@ impl Instruction {
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12
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}
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}
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JpCond::Always => {
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JumpCondition::Always => {
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cpu.bus.clock(); // internal branch decision
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Self::push(cpu, return_addr);
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cpu.set_register_pair(RegisterPair::PC, addr);
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@ -1538,7 +1538,7 @@ impl Instruction {
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}
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impl Instruction {
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pub(crate) fn decode(byte: u8, prefixed: bool) -> Option<Self> {
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pub(crate) fn decode(byte: u8, prefixed: bool) -> Self {
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if prefixed {
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Self::prefixed(byte)
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} else {
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|
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@ -1546,139 +1546,134 @@ impl Instruction {
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}
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}
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fn unprefixed(byte: u8) -> Option<Self> {
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fn unprefixed(byte: u8) -> Self {
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use Instruction::*;
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match byte {
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// NOP
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0o000 => Some(NOP),
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0o000 => NOP,
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// LD (u16), SP
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0o010 => Some(LD(LDTarget::IndirectImmediateWord, LDSource::SP)),
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0o010 => LD(LDTarget::IndirectImmediateWord, LDSource::SP),
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// STOP
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0o020 => Some(STOP),
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0o020 => STOP,
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// JR i8
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0o030 => Some(JR(JpCond::Always)),
|
||||
0o030 => JR(JumpCondition::Always),
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||||
// JR cond i8
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||||
0o040 | 0o050 | 0o060 | 0o070 => Some(JR(jump_cond((byte >> 3) & 0x03))),
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0o040 | 0o050 | 0o060 | 0o070 => JR(jump_cond((byte >> 3) & 0x03)),
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// LD r16, u16
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0o001 | 0o021 | 0o041 | 0o061 => Some(LD(
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||||
0o001 | 0o021 | 0o041 | 0o061 => LD(
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LDTarget::Group1(group1((byte >> 4) & 0x03)),
|
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LDSource::ImmediateWord,
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||||
)),
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||||
),
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||||
// ADD HL, r16
|
||||
0o011 | 0o031 | 0o051 | 0o071 => Some(ADD(
|
||||
AddTarget::HL,
|
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AddSource::Group1(group1((byte >> 4) & 0x03)),
|
||||
)),
|
||||
0o011 | 0o031 | 0o051 | 0o071 => {
|
||||
ADD(AddTarget::HL, AddSource::Group1(group1((byte >> 4) & 0x03)))
|
||||
}
|
||||
// LD (r16), A
|
||||
0o002 | 0o022 | 0o042 | 0o062 => Some(LD(
|
||||
0o002 | 0o022 | 0o042 | 0o062 => LD(
|
||||
LDTarget::IndirectGroup2(group2((byte >> 4) & 0x03)),
|
||||
LDSource::A,
|
||||
)),
|
||||
),
|
||||
// LD A, (r16)
|
||||
0o012 | 0o032 | 0o052 | 0o072 => Some(LD(
|
||||
0o012 | 0o032 | 0o052 | 0o072 => LD(
|
||||
LDTarget::A,
|
||||
LDSource::IndirectGroup2(group2((byte >> 4) & 0x03)),
|
||||
)),
|
||||
),
|
||||
// INC r16
|
||||
0o003 | 0o023 | 0o043 | 0o063 => {
|
||||
Some(INC(AllRegisters::Group1(group1((byte >> 4) & 0x03))))
|
||||
}
|
||||
0o003 | 0o023 | 0o043 | 0o063 => INC(AllRegisters::Group1(group1((byte >> 4) & 0x03))),
|
||||
// DEC r16
|
||||
0o013 | 0o033 | 0o053 | 0o073 => {
|
||||
Some(DEC(AllRegisters::Group1(group1((byte >> 4) & 0x03))))
|
||||
}
|
||||
0o013 | 0o033 | 0o053 | 0o073 => DEC(AllRegisters::Group1(group1((byte >> 4) & 0x03))),
|
||||
// INC r8
|
||||
0o004 | 0o014 | 0o024 | 0o034 | 0o044 | 0o054 | 0o064 | 0o074 => {
|
||||
Some(INC(AllRegisters::Register(register((byte >> 3) & 0x07))))
|
||||
INC(AllRegisters::Register(register((byte >> 3) & 0x07)))
|
||||
}
|
||||
// DEC r8
|
||||
0o005 | 0o015 | 0o025 | 0o035 | 0o045 | 0o055 | 0o065 | 0o075 => {
|
||||
Some(DEC(AllRegisters::Register(register((byte >> 3) & 0x07))))
|
||||
DEC(AllRegisters::Register(register((byte >> 3) & 0x07)))
|
||||
}
|
||||
// LD r8, u8
|
||||
0o006 | 0o016 | 0o026 | 0o036 | 0o046 | 0o056 | 0o066 | 0o076 => Some(LD(
|
||||
0o006 | 0o016 | 0o026 | 0o036 | 0o046 | 0o056 | 0o066 | 0o076 => LD(
|
||||
LDTarget::Register(register((byte >> 3) & 0x07)),
|
||||
LDSource::ImmediateByte,
|
||||
)),
|
||||
),
|
||||
// RLCA, RRCA, RLA, RRA, DAA, CPL, SCF, and CCF
|
||||
0o007 | 0o017 | 0o027 | 0o037 | 0o047 | 0o057 | 0o067 | 0o077 => {
|
||||
Some(flag_instr((byte >> 3) & 0x07))
|
||||
flag_instr((byte >> 3) & 0x07)
|
||||
}
|
||||
// HALT
|
||||
0o166 => Some(HALT),
|
||||
0o166 => HALT,
|
||||
// LD r8, r8
|
||||
0o100..=0o177 => Some(LD(
|
||||
0o100..=0o177 => LD(
|
||||
LDTarget::Register(register((byte >> 3) & 0x07)),
|
||||
LDSource::Register(register(byte & 0x07)),
|
||||
)),
|
||||
),
|
||||
// ADD, ADC, SUB, SBC, AND, XOR, OR, and CP
|
||||
0o200..=0o277 => Some(alu_reg_instr((byte >> 3) & 0x07, byte & 0x07)),
|
||||
0o200..=0o277 => alu_reg_instr((byte >> 3) & 0x07, byte & 0x07),
|
||||
// RET cond
|
||||
0o300 | 0o310 | 0o320 | 0o330 => Some(RET(jump_cond((byte >> 3) & 0x03))),
|
||||
0o300 | 0o310 | 0o320 | 0o330 => RET(jump_cond((byte >> 3) & 0x03)),
|
||||
// LD (0xFF00 + u8), A
|
||||
0o340 => Some(LD(LDTarget::IoWithImmediateOffset, LDSource::A)),
|
||||
0o340 => LD(LDTarget::IoWithImmediateOffset, LDSource::A),
|
||||
// ADD SP, i8
|
||||
0o350 => Some(ADD(AddTarget::SP, AddSource::ImmediateSignedByte)),
|
||||
0o350 => ADD(AddTarget::SP, AddSource::ImmediateSignedByte),
|
||||
// LD A, (0xFF00 + u8)
|
||||
0o360 => Some(LD(LDTarget::A, LDSource::IoWithImmediateOffset)),
|
||||
0o360 => LD(LDTarget::A, LDSource::IoWithImmediateOffset),
|
||||
// LD HL, SP + i8
|
||||
0o370 => Some(LDHL),
|
||||
0o370 => LDHL,
|
||||
// POP r16
|
||||
0o301 | 0o321 | 0o341 | 0o361 => Some(POP(group3((byte >> 4) & 0x03))),
|
||||
0o301 | 0o321 | 0o341 | 0o361 => POP(group3((byte >> 4) & 0x03)),
|
||||
// RET
|
||||
0o311 => Some(RET(JpCond::Always)),
|
||||
0o311 => RET(JumpCondition::Always),
|
||||
// RETI
|
||||
0o331 => Some(RETI),
|
||||
0o331 => RETI,
|
||||
// JP HL
|
||||
0o351 => Some(JP(JpCond::Always, JpLoc::HL)),
|
||||
0o351 => JP(JumpCondition::Always, JumpLocation::HL),
|
||||
// LD SP, HL
|
||||
0o371 => Some(LD(LDTarget::SP, LDSource::HL)),
|
||||
0o371 => LD(LDTarget::SP, LDSource::HL),
|
||||
// JP cond u16
|
||||
0o302 | 0o312 | 0o322 | 0o332 => {
|
||||
Some(JP(jump_cond((byte >> 3) & 0x03), JpLoc::ImmediateWord))
|
||||
JP(jump_cond((byte >> 3) & 0x03), JumpLocation::ImmediateWord)
|
||||
}
|
||||
// LD (0xFF00 + C), A
|
||||
0o342 => Some(LD(LDTarget::IoWithC, LDSource::A)),
|
||||
0o342 => LD(LDTarget::IoWithC, LDSource::A),
|
||||
// LD (u16), A
|
||||
0o352 => Some(LD(LDTarget::IndirectImmediateWord, LDSource::A)),
|
||||
0o352 => LD(LDTarget::IndirectImmediateWord, LDSource::A),
|
||||
// LD A, (0xFF00 + C)
|
||||
0o362 => Some(LD(LDTarget::A, LDSource::IoWithC)),
|
||||
0o362 => LD(LDTarget::A, LDSource::IoWithC),
|
||||
// LD A, (u16)
|
||||
0o372 => Some(LD(LDTarget::A, LDSource::IndirectImmediateWord)),
|
||||
0o372 => LD(LDTarget::A, LDSource::IndirectImmediateWord),
|
||||
// JP u16
|
||||
0o303 => Some(JP(JpCond::Always, JpLoc::ImmediateWord)),
|
||||
0o303 => JP(JumpCondition::Always, JumpLocation::ImmediateWord),
|
||||
// 0xCB Prefix
|
||||
0o313 => unreachable!("{:#04X} should be handled by the prefixed decoder", byte),
|
||||
// DI
|
||||
0o363 => Some(DI),
|
||||
0o363 => DI,
|
||||
// EI
|
||||
0o373 => Some(EI),
|
||||
0o373 => EI,
|
||||
// CALL cond u16
|
||||
0o304 | 0o314 | 0o324 | 0o334 => Some(CALL(jump_cond((byte >> 3) & 0x03))),
|
||||
0o304 | 0o314 | 0o324 | 0o334 => CALL(jump_cond((byte >> 3) & 0x03)),
|
||||
// PUSH r16
|
||||
0o305 | 0o325 | 0o345 | 0o365 => Some(PUSH(group3((byte >> 4) & 0x03))),
|
||||
0o315 => Some(CALL(JpCond::Always)),
|
||||
0o305 | 0o325 | 0o345 | 0o365 => PUSH(group3((byte >> 4) & 0x03)),
|
||||
0o315 => CALL(JumpCondition::Always),
|
||||
0o306 | 0o316 | 0o326 | 0o336 | 0o346 | 0o356 | 0o366 | 0o376 => {
|
||||
Some(alu_imm_instr((byte >> 3) & 0x07))
|
||||
alu_imm_instr((byte >> 3) & 0x07)
|
||||
}
|
||||
0o307 | 0o317 | 0o327 | 0o337 | 0o347 | 0o357 | 0o367 | 0o377 => {
|
||||
Some(RST(byte & 0b00111000))
|
||||
}
|
||||
_ => None, // 0xCB is 0o313
|
||||
0o307 | 0o317 | 0o327 | 0o337 | 0o347 | 0o357 | 0o367 | 0o377 => RST(byte & 0b00111000),
|
||||
_ => panic!("{:#04X} is an illegal opcode", byte),
|
||||
}
|
||||
}
|
||||
|
||||
fn prefixed(byte: u8) -> Option<Self> {
|
||||
fn prefixed(byte: u8) -> Self {
|
||||
use Instruction::*;
|
||||
|
||||
match byte {
|
||||
// RLC, RRC, RL, RR, SLA, SRA, SWAP and SRL
|
||||
0o000..=0o077 => Some(prefix_alu((byte >> 3) & 0x07, byte & 0x07)),
|
||||
0o000..=0o077 => prefix_alu((byte >> 3) & 0x07, byte & 0x07),
|
||||
// BIT bit, r8
|
||||
0o100..=0o177 => Some(BIT((byte >> 3) & 0x07, register(byte & 0x07))),
|
||||
0o100..=0o177 => BIT((byte >> 3) & 0x07, register(byte & 0x07)),
|
||||
// RES bit, r8
|
||||
0o200..=0o277 => Some(RES((byte >> 3) & 0x07, register(byte & 0x07))),
|
||||
0o200..=0o277 => RES((byte >> 3) & 0x07, register(byte & 0x07)),
|
||||
// SET bit, r8
|
||||
0o300..=0o377 => Some(SET((byte >> 3) & 0x07, register(byte & 0x07))),
|
||||
0o300..=0o377 => SET((byte >> 3) & 0x07, register(byte & 0x07)),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1686,7 +1681,7 @@ impl Instruction {
|
|||
mod jump {
|
||||
|
||||
#[derive(Clone, Copy)]
|
||||
pub(crate) enum JpCond {
|
||||
pub(crate) enum JumpCondition {
|
||||
Always,
|
||||
NotZero,
|
||||
Zero,
|
||||
|
|
@ -1694,9 +1689,9 @@ mod jump {
|
|||
Carry,
|
||||
}
|
||||
|
||||
impl std::fmt::Debug for JpCond {
|
||||
impl std::fmt::Debug for JumpCondition {
|
||||
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
|
||||
use JpCond::*;
|
||||
use JumpCondition::*;
|
||||
|
||||
match self {
|
||||
Always => f.write_str(""),
|
||||
|
|
@ -1709,14 +1704,14 @@ mod jump {
|
|||
}
|
||||
|
||||
#[derive(Clone, Copy)]
|
||||
pub(crate) enum JpLoc {
|
||||
pub(crate) enum JumpLocation {
|
||||
HL,
|
||||
ImmediateWord,
|
||||
}
|
||||
|
||||
impl std::fmt::Debug for JpLoc {
|
||||
impl std::fmt::Debug for JumpLocation {
|
||||
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
|
||||
use JpLoc::*;
|
||||
use JumpLocation::*;
|
||||
|
||||
match *self {
|
||||
HL => f.write_str("HL"),
|
||||
|
|
@ -1876,7 +1871,7 @@ mod load {
|
|||
mod table {
|
||||
use super::add::{Source as AddSource, Target as AddTarget};
|
||||
use super::alu::Source as AluSource;
|
||||
use super::{Instruction, JpCond};
|
||||
use super::{Instruction, JumpCondition};
|
||||
use crate::cpu::{Register as CpuRegister, RegisterPair};
|
||||
|
||||
#[derive(Clone, Copy)]
|
||||
|
|
@ -2079,8 +2074,8 @@ mod table {
|
|||
}
|
||||
}
|
||||
|
||||
pub(crate) fn jump_cond(code: u8) -> JpCond {
|
||||
use JpCond::*;
|
||||
pub(crate) fn jump_cond(code: u8) -> JumpCondition {
|
||||
use JumpCondition::*;
|
||||
|
||||
match code {
|
||||
0b00 => NotZero,
|
||||
|
|
@ -2158,7 +2153,7 @@ mod table {
|
|||
|
||||
pub(crate) mod dbg {
|
||||
use super::add::{Source as AddSource, Target as AddTarget};
|
||||
use super::jump::JpCond;
|
||||
use super::jump::JumpCondition;
|
||||
use super::load::{Source as LDSource, Target as LDTarget};
|
||||
use super::{AllRegisters, BusIo, Cpu, Instruction, RegisterPair};
|
||||
|
||||
|
|
@ -2170,7 +2165,7 @@ pub(crate) mod dbg {
|
|||
let opcode = cpu.read_byte(pc);
|
||||
pc += 1;
|
||||
|
||||
let maybe_instr = if opcode == 0xCB {
|
||||
let instr = if opcode == 0xCB {
|
||||
let opcode = cpu.read_byte(pc);
|
||||
pc += 1;
|
||||
|
||||
|
|
@ -2179,13 +2174,11 @@ pub(crate) mod dbg {
|
|||
Instruction::unprefixed(opcode)
|
||||
};
|
||||
|
||||
if let Some(instr) = maybe_instr {
|
||||
let instr_asm = format!("{:04X} {:?}\n", pc - 1, instr);
|
||||
asm.push_str(&instr_asm);
|
||||
|
||||
pc += delta::pc_inc_count(instr)
|
||||
}
|
||||
}
|
||||
|
||||
asm
|
||||
}
|
||||
|
|
@ -2197,12 +2190,12 @@ pub(crate) mod dbg {
|
|||
let imm_word = (cpu.read_byte(pc + 2) as u16) << 8 | imm_byte as u16;
|
||||
|
||||
match instr {
|
||||
NOP => "NOP".to_string(),
|
||||
NOP => format!("NOP"),
|
||||
LD(LDTarget::IndirectImmediateWord, LDSource::SP) => {
|
||||
format!("LD ({:#06X}), SP", imm_word)
|
||||
}
|
||||
STOP => "STOP".to_string(),
|
||||
JR(JpCond::Always) => format!("JR {}", imm_byte as i8),
|
||||
STOP => format!("STOP"),
|
||||
JR(JumpCondition::Always) => format!("JR {}", imm_byte as i8),
|
||||
JR(cond) => format!("JR {:?} {}", cond, imm_byte as i8),
|
||||
LD(LDTarget::Group1(rp), LDSource::ImmediateWord) => {
|
||||
format!("LD {:?} {:#06X}", rp, imm_word)
|
||||
|
|
@ -2218,7 +2211,7 @@ pub(crate) mod dbg {
|
|||
mod delta {
|
||||
use super::super::add::{Source as AddSource, Target as AddTarget};
|
||||
use super::super::alu::Source as AluSource;
|
||||
use super::super::jump::{JpCond, JpLoc};
|
||||
use super::super::jump::{JumpCondition, JumpLocation};
|
||||
use super::super::load::{Source as LDSource, Target as LDTarget};
|
||||
use super::super::{AllRegisters, Instruction};
|
||||
|
||||
|
|
@ -2265,9 +2258,9 @@ pub(crate) mod dbg {
|
|||
LDHL => 1,
|
||||
POP(_) => 0,
|
||||
RETI => 0,
|
||||
JP(JpCond::Always, JpLoc::HL) => 0,
|
||||
JP(JumpCondition::Always, JumpLocation::HL) => 0,
|
||||
LD(LDTarget::SP, LDSource::HL) => 0,
|
||||
JP(_, JpLoc::ImmediateWord) => 2,
|
||||
JP(_, JumpLocation::ImmediateWord) => 2,
|
||||
LD(LDTarget::IoWithC, LDSource::A) => 0,
|
||||
LD(LDTarget::IndirectImmediateWord, LDSource::A) => 2,
|
||||
LD(LDTarget::A, LDSource::IoWithC) => 0,
|
||||
|
|
|
|||
Loading…
Reference in New Issue