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base: paoda:9973dc8714d84f473aa604cd74dc3656f9d76d5f
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paoda:main
paoda:refactor
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compare: paoda:44ac0c8ebd23f376f1df6e74d31c0204060b9d3f
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paoda:main
paoda:refactor

No commits in common. "9973dc8714d84f473aa604cd74dc3656f9d76d5f" and "44ac0c8ebd23f376f1df6e74d31c0204060b9d3f" have entirely different histories.
9973dc8714 ... 44ac0c8ebd

1 changed files with 26 additions and 16 deletions
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42
src/cartridge.rs
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@ -188,16 +188,16 @@ impl MBC1 {
} }
} }
fn ram_addr(&self, addr: u16) -> usize { fn ram_addr(&self, addr: u16) -> u16 {
use RamSize::*; use RamSize::*;
match self.ram_size { match self.ram_size {
Unused | One => (addr as usize - 0xA000) % self.ram_size.capacity(), Unused | One => (addr - 0xA000) % self.ram_size.capacity() as u16,
Four => { Four => {
if self.mode { if self.mode {
0x2000 * self.ram_bank as usize + (addr as usize - 0xA000) 0x2000 * self.ram_bank as u16 + (addr - 0xA000)
} else { } else {
addr as usize - 0xA000 addr - 0xA000
} }
} }
_ => unreachable!("RAM size can not be greater than 32KB on MBC1"), _ => unreachable!("RAM size can not be greater than 32KB on MBC1"),
@ -210,17 +210,23 @@ impl MBCIo for MBC1 {
use MBCResult::*; use MBCResult::*;
match addr { match addr {
0x0000..=0x3FFF if self.mode => { 0x0000..=0x3FFF => {
Address(0x4000 * self.zero_bank() as usize + addr as usize) if self.mode {
Address(0x4000 * self.zero_bank() as usize + addr as usize)
} else {
Address(addr as usize)
}
} }
0x0000..=0x3FFF => Address(addr as usize),
0x4000..=0x7FFF => { 0x4000..=0x7FFF => {
Address(0x4000 * self.high_bank() as usize + (addr as usize - 0x4000)) Address(0x4000 * self.high_bank() as usize + (addr as usize - 0x4000))
} }
0xA000..=0xBFFF if self.mem_enabled && self.ram_size != RamSize::None => { 0xA000..=0xBFFF => {
Value(self.memory[self.ram_addr(addr)]) if self.mem_enabled {
Value(self.memory[self.ram_addr(addr) as usize])
} else {
Value(0xFF)
}
} }
0xA000..=0xBFFF => Value(0xFF),
_ => unreachable!("A read from {:#06X} should not be handled by MBC1", addr), _ => unreachable!("A read from {:#06X} should not be handled by MBC1", addr),
} }
} }
@ -229,14 +235,18 @@ impl MBCIo for MBC1 {
match addr { match addr {
0x0000..=0x1FFF => self.mem_enabled = (byte & 0x0F) == 0x0A, 0x0000..=0x1FFF => self.mem_enabled = (byte & 0x0F) == 0x0A,
0x2000..=0x3FFF => { 0x2000..=0x3FFF => {
let value = byte & 0x1F; self.rom_bank = if byte == 0x00 {
let masked_value = byte & self.rom_size_mask(); 0x01
self.rom_bank = if value == 0 { 0x01 } else { masked_value }; } else {
byte & self.rom_size_mask()
};
self.rom_bank &= 0x1F;
} }
0x4000..=0x5FFF => self.ram_bank = byte & 0x03, 0x4000..=0x5FFF => self.ram_bank = byte & 0x03,
0x6000..=0x7FFF => self.mode = (byte & 0x01) == 0x01, 0x6000..=0x7FFF => self.mode = (byte & 0x01) == 0x01,
0xA000..=0xBFFF if self.mem_enabled && self.ram_size != RamSize::None => { 0xA000..=0xBFFF if self.mem_enabled => {
let ram_addr = self.ram_addr(addr); let ram_addr = self.ram_addr(addr) as usize;
self.memory[ram_addr] = byte; self.memory[ram_addr] = byte;
} }
0xA000..=0xBFFF => {} // Ram isn't enabled, ignored write 0xA000..=0xBFFF => {} // Ram isn't enabled, ignored write
@ -505,7 +515,7 @@ impl Default for MBCKind {
} }
} }
#[derive(Debug, Clone, Copy, PartialEq)] #[derive(Debug, Clone, Copy)]
enum RamSize { enum RamSize {
None = 0x00, None = 0x00,
Unused = 0x01, Unused = 0x01,