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2 Commits
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9973dc8714
Author | SHA1 | Date |
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Rekai Nyangadzayi Musuka | 9973dc8714 | |
Rekai Nyangadzayi Musuka | e128025208 |
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@ -188,16 +188,16 @@ impl MBC1 {
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}
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}
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fn ram_addr(&self, addr: u16) -> u16 {
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fn ram_addr(&self, addr: u16) -> usize {
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use RamSize::*;
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match self.ram_size {
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Unused | One => (addr - 0xA000) % self.ram_size.capacity() as u16,
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Unused | One => (addr as usize - 0xA000) % self.ram_size.capacity(),
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Four => {
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if self.mode {
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0x2000 * self.ram_bank as u16 + (addr - 0xA000)
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0x2000 * self.ram_bank as usize + (addr as usize - 0xA000)
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} else {
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addr - 0xA000
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addr as usize - 0xA000
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}
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}
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_ => unreachable!("RAM size can not be greater than 32KB on MBC1"),
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@ -210,23 +210,17 @@ impl MBCIo for MBC1 {
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use MBCResult::*;
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match addr {
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0x0000..=0x3FFF => {
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if self.mode {
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0x0000..=0x3FFF if self.mode => {
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Address(0x4000 * self.zero_bank() as usize + addr as usize)
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} else {
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Address(addr as usize)
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}
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}
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0x0000..=0x3FFF => Address(addr as usize),
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0x4000..=0x7FFF => {
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Address(0x4000 * self.high_bank() as usize + (addr as usize - 0x4000))
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}
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0xA000..=0xBFFF => {
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if self.mem_enabled {
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Value(self.memory[self.ram_addr(addr) as usize])
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} else {
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Value(0xFF)
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}
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0xA000..=0xBFFF if self.mem_enabled && self.ram_size != RamSize::None => {
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Value(self.memory[self.ram_addr(addr)])
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}
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0xA000..=0xBFFF => Value(0xFF),
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_ => unreachable!("A read from {:#06X} should not be handled by MBC1", addr),
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}
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}
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@ -235,18 +229,14 @@ impl MBCIo for MBC1 {
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match addr {
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0x0000..=0x1FFF => self.mem_enabled = (byte & 0x0F) == 0x0A,
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0x2000..=0x3FFF => {
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self.rom_bank = if byte == 0x00 {
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0x01
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} else {
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byte & self.rom_size_mask()
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};
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self.rom_bank &= 0x1F;
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let value = byte & 0x1F;
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let masked_value = byte & self.rom_size_mask();
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self.rom_bank = if value == 0 { 0x01 } else { masked_value };
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}
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0x4000..=0x5FFF => self.ram_bank = byte & 0x03,
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0x6000..=0x7FFF => self.mode = (byte & 0x01) == 0x01,
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0xA000..=0xBFFF if self.mem_enabled => {
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let ram_addr = self.ram_addr(addr) as usize;
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0xA000..=0xBFFF if self.mem_enabled && self.ram_size != RamSize::None => {
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let ram_addr = self.ram_addr(addr);
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self.memory[ram_addr] = byte;
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}
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0xA000..=0xBFFF => {} // Ram isn't enabled, ignored write
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@ -515,7 +505,7 @@ impl Default for MBCKind {
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}
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}
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#[derive(Debug, Clone, Copy)]
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#[derive(Debug, Clone, Copy, PartialEq)]
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enum RamSize {
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None = 0x00,
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Unused = 0x01,
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