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No commits in common. "4125ea5c74bdef91004f637489165d8bd5cefe09" and "01278ca83f5d80751c5bd4e66577091f5beb1864" have entirely different histories.

2 changed files with 8 additions and 14 deletions

View File

@ -262,7 +262,6 @@ impl BusIo for Bus {
0x49 => self.ppu.monochrome.obj_palette_1.into(),
0x4A => self.ppu.pos.window_y,
0x4B => self.ppu.pos.window_x,
0x4F => 0xFF, // CGB VRAM Bank Select
_ => {
warn!("Attempted read from {:#06X} on IO", addr);
0xFF
@ -373,14 +372,12 @@ impl BusIo for Bus {
0x4A => self.ppu.pos.window_y = byte,
0x4B => self.ppu.pos.window_x = byte,
0x4D => {} // CGB Specific Register
0x4F => {} // CGB VRAM Bank Select
0x50 => {
// Disable Boot ROM
if byte != 0 {
self.boot = None;
}
}
0x70 => {} // CGB WRAM Bank Select
_ => warn!("Attempted write of {:#04X} to {:#06X} on IO", byte, addr),
};
}

View File

@ -334,6 +334,7 @@ impl Instruction {
Instruction::ADD(target, src) => match (target, src) {
(AddTarget::HL, AddSource::Group1(pair)) => {
// ADD HL, r16 | Add 16-bit register to HL
// FIXME: Memory Timings are not properly emulated for this instruction
use Group1RegisterPair::*;
let mut flags: Flags = *cpu.flags();
@ -341,11 +342,10 @@ impl Instruction {
BC | DE | HL | SP => {
let left = cpu.register_pair(RegisterPair::HL);
let right = cpu.register_pair(pair.as_register_pair());
let result = Self::add_u16(left, right, &mut flags);
cpu.set_register(CpuRegister::L, result as u8);
cpu.bus.clock();
cpu.set_register(CpuRegister::H, (result >> 8) as u8);
cpu.set_register_pair(
RegisterPair::HL,
Self::add_u16(left, right, &mut flags),
);
}
}
cpu.set_flags(flags);
@ -376,15 +376,12 @@ impl Instruction {
}
(AddTarget::SP, AddSource::ImmediateSignedByte) => {
// ADD SP, i8 | Add i8 to stack pointer
// FIXME: Memory Timings are not properly emulated for this instruction
let mut flags: Flags = *cpu.flags();
let left = cpu.register_pair(RegisterPair::SP);
let sum = Self::add_u16_i8(left, Self::imm_byte(cpu) as i8, &mut flags);
cpu.bus.clock(); // internal
cpu.set_register_pair(RegisterPair::SP, sum);
cpu.bus.clock();
cpu.set_flags(flags);
16
}
@ -426,6 +423,7 @@ impl Instruction {
AllRegisters::Group1(pair) => {
// INC r16 | Increment 16-bit register
// Note: No flags are set with this version of the INC instruction
// FIXME: Memory Timings are not properly emulated for this instruction
use Group1RegisterPair::*;
match pair {
@ -433,7 +431,6 @@ impl Instruction {
let pair = pair.as_register_pair();
let left = cpu.register_pair(pair);
cpu.set_register_pair(pair, left.wrapping_add(1));
cpu.bus.clock(); // internal
}
}
8
@ -465,6 +462,7 @@ impl Instruction {
}
AllRegisters::Group1(pair) => {
// DEC r16 | Decrement Register Pair
// FIXME: Memory Timings are not properly emulated for this instruction
use Group1RegisterPair::*;
match pair {
@ -472,7 +470,6 @@ impl Instruction {
let pair = pair.as_register_pair();
let left = cpu.register_pair(pair);
cpu.set_register_pair(pair, left.wrapping_sub(1));
cpu.bus.clock(); // internal
}
};
8