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2 Commits

Author SHA1 Message Date
Rekai Nyangadzayi Musuka d794a94b68 fix(timer): increase accuracy of timer
continuous-integration/drone/push Build is passing Details
2021-08-20 00:17:28 -05:00
Rekai Nyangadzayi Musuka b87e31d3f4 fix(cartridge): remove unnecessary dbg statement 2021-08-20 00:17:05 -05:00
2 changed files with 39 additions and 15 deletions

View File

@ -75,7 +75,7 @@ impl Cartridge {
} }
fn detect_rom_info(memory: &[u8]) -> RomSize { fn detect_rom_info(memory: &[u8]) -> RomSize {
let id = dbg!(memory[ROM_SIZE_ADDRESS]); let id = memory[ROM_SIZE_ADDRESS];
id.into() id.into()
} }

View File

@ -21,18 +21,29 @@ impl Timer {
use State::*; use State::*;
use TimerSpeed::*; use TimerSpeed::*;
if let TIMAOverflow(step) | AbortedTIMAOverflow(step) = self.state { match self.state {
if step < 4 { TIMAOverflow(_) | AbortedTIMAOverflow(_) => self.state = self.state.next(),
self.state = TIMAOverflow(step + 1); LoadTMA => {
return; self.counter = self.modulo;
self.interrupt = true;
self.state.next();
}
Normal => {}
} }
if let TIMAOverflow(step) | AbortedTIMAOverflow(step) = self.state {
if step < 3 {
self.state = self.state.next();
} else {
if self.state == TIMAOverflow(step) { if self.state == TIMAOverflow(step) {
self.counter = self.modulo; self.counter = self.modulo;
self.interrupt = true; self.interrupt = true;
} }
self.state = Normal; self.state = Normal;
} }
}
self.divider = self.divider.wrapping_add(1); self.divider = self.divider.wrapping_add(1);
@ -67,14 +78,12 @@ impl Timer {
use State::*; use State::*;
match self.state { match self.state {
Normal => self.counter = byte, Normal | AbortedTIMAOverflow(_) => self.counter = byte,
TIMAOverflow(step) => { TIMAOverflow(step) => {
if step < 4 {
self.counter = byte; self.counter = byte;
self.state = AbortedTIMAOverflow(step); self.state = AbortedTIMAOverflow(step);
} }
} LoadTMA => {}
AbortedTIMAOverflow(_) => self.counter = byte,
} }
} }
@ -173,4 +182,19 @@ enum State {
TIMAOverflow(u8), TIMAOverflow(u8),
AbortedTIMAOverflow(u8), AbortedTIMAOverflow(u8),
Normal, Normal,
LoadTMA,
}
impl State {
fn next(&self) -> Self {
use State::*;
match self {
Normal | LoadTMA => Normal,
TIMAOverflow(3) => LoadTMA,
AbortedTIMAOverflow(3) => Normal,
TIMAOverflow(step) => TIMAOverflow(step + 1),
AbortedTIMAOverflow(step) => AbortedTIMAOverflow(step + 1),
}
}
} }