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cf2357f917
| Author | SHA1 | Date |
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 Rekai Nyangadzayi Musuka
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cf2357f917 | |
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Rekai Nyangadzayi Musuka
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3fb7edd333 |
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@ -1654,7 +1654,9 @@ impl Instruction {
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0o304 | 0o314 | 0o324 | 0o334 => CALL(jump_cond((byte >> 3) & 0x03)),
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// PUSH r16
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0o305 | 0o325 | 0o345 | 0o365 => PUSH(group3((byte >> 4) & 0x03)),
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// CALL u16
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0o315 => CALL(JpCond::Always),
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// ADD, ADC, SUB, SBC, AND, XOR, OR, and CP
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0o306 | 0o316 | 0o326 | 0o336 | 0o346 | 0o356 | 0o366 | 0o376 => {
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alu_imm_instr((byte >> 3) & 0x07)
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}
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@ -2153,8 +2155,11 @@ mod table {
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}
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pub(crate) mod dbg {
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use std::borrow::Cow;
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use super::add::{Source as AddSource, Target as AddTarget};
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use super::jump::JpCond;
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use super::alu::Source as AluSource;
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use super::jump::{JpCond, JpLoc};
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use super::load::{Source as LDSource, Target as LDTarget};
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use super::{AllRegisters, BusIo, Cpu, Instruction, RegisterPair};
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@ -2188,28 +2193,140 @@ pub(crate) mod dbg {
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sm83_asm
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}
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fn disasm(cpu: &Cpu, pc: u16, instr: Instruction) -> String {
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pub(crate) fn new_disasm(cpu: &Cpu, limit: u8) -> String {
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let mut assembly = String::new();
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let mut pc = cpu.register_pair(RegisterPair::PC);
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for _ in 0..limit {
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let opcode = cpu.read_byte(pc);
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pc += 1;
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let maybe_instr = if opcode == 0xCB {
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let opcode = cpu.read_byte(pc);
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pc += 1;
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Instruction::prefixed(opcode)
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} else {
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Instruction::unprefixed(opcode)
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};
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match maybe_instr {
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Instruction::Invalid => {}
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instr => {
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let output = format!("${:04X} {}\n", pc - 1, disasm(cpu, pc, instr));
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assembly.push_str(&output);
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pc += delta::pc_inc_count(instr);
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}
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}
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}
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assembly
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}
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// TODO: It might be better if I pass in a mutable writer instead of usnig a String
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fn disasm(cpu: &Cpu, pc: u16, instr: Instruction) -> Cow<str> {
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use Instruction::*;
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let imm_byte = cpu.read_byte(pc + 1);
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let imm_word = (cpu.read_byte(pc + 2) as u16) << 8 | imm_byte as u16;
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match instr {
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NOP => "NOP".to_string(),
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// Unprefixed Instructions
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NOP => "NOP".into(),
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LD(LDTarget::IndirectImmediateWord, LDSource::SP) => {
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format!("LD ({:#06X}), SP", imm_word)
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format!("LD ({:#06X}), SP", imm_word).into()
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}
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STOP => "STOP".to_string(),
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JR(JpCond::Always) => format!("JR {}", imm_byte as i8),
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JR(cond) => format!("JR {:?} {}", cond, imm_byte as i8),
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STOP => "STOP".into(),
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JR(JpCond::Always) => format!("JR {}", imm_byte as i8).into(),
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JR(cond) => format!("JR {:?} {}", cond, imm_byte as i8).into(),
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LD(LDTarget::Group1(rp), LDSource::ImmediateWord) => {
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format!("LD {:?} {:#06X}", rp, imm_word)
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format!("LD {:?} {:#06X}", rp, imm_word).into()
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}
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ADD(AddTarget::HL, AddSource::Group1(rp)) => format!("ADD HL, {:?}", rp),
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LD(LDTarget::IndirectGroup2(rp), LDSource::A) => format!("LD ({:?}), A", rp),
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LD(LDTarget::A, LDSource::IndirectGroup2(rp)) => format!("LD A, ({:?})", rp),
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ADD(AddTarget::HL, AddSource::Group1(rp)) => format!("ADD HL, {:?}", rp).into(),
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LD(LDTarget::IndirectGroup2(rp), LDSource::A) => format!("LD ({:?}), A", rp).into(),
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LD(LDTarget::A, LDSource::IndirectGroup2(rp)) => format!("LD A, ({:?})", rp).into(),
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INC(AllRegisters::Group1(rp)) => format!("INC {:?}", rp).into(),
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DEC(AllRegisters::Group1(rp)) => format!("DEC {:?}", rp).into(),
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INC(AllRegisters::Register(reg)) => format!("INC {:?}", reg).into(),
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DEC(AllRegisters::Register(reg)) => format!("DEC {:?}", reg).into(),
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LD(LDTarget::Register(reg), LDSource::ImmediateByte) => {
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format!("LD {:?}, {:#04X}", reg, imm_byte).into()
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}
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RLCA => "RLCA".into(),
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RRCA => "RRCA".into(),
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RLA => "RLA".into(),
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RRA => "RRA".into(),
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DAA => "DAA".into(),
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CPL => "CPL".into(),
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SCF => "SCF".into(),
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CCF => "CCF".into(),
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HALT => "HALT".into(),
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LD(LDTarget::Register(left), LDSource::Register(right)) => {
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format!("LD {:?}, {:?}", left, right).into()
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}
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ADD(AddTarget::A, AddSource::Register(reg)) => format!("ADD A, {:?}", reg).into(),
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ADC(AluSource::Register(reg)) => format!("ADC {:?}", reg).into(),
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SUB(AluSource::Register(reg)) => format!("SUB {:?}", reg).into(),
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SBC(AluSource::Register(reg)) => format!("SBC {:?}", reg).into(),
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AND(AluSource::Register(reg)) => format!("AND {:?}", reg).into(),
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XOR(AluSource::Register(reg)) => format!("XOR {:?}", reg).into(),
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OR(AluSource::Register(reg)) => format!("OR {:?}", reg).into(),
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CP(AluSource::Register(reg)) => format!("CP {:?}", reg).into(),
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RET(JpCond::Always) => "RET".into(),
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RET(cond) => format!("RET {:?}", cond).into(),
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LD(LDTarget::IoWithImmediateOffset, LDSource::A) => {
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format!("LD ({:#06X}) , A", 0xFF00 + imm_byte as u16).into()
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}
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ADD(AddTarget::SP, AddSource::ImmediateSignedByte) => {
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format!("ADD SP, {}", imm_byte as i8).into()
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}
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LD(LDTarget::A, LDSource::IoWithImmediateOffset) => {
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format!("LD A, ({:#06X})", 0xFF00 + imm_byte as u16).into()
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}
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LDHL => format!("LD HL, SP + {}", imm_byte as i8).into(),
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POP(rp) => format!("POP {:?}", rp).into(),
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RETI => "RETI".into(),
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JP(JpCond::Always, JpLoc::HL) => "JP HL".into(),
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LD(LDTarget::SP, LDSource::HL) => "LD SP, HL".into(),
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JP(JpCond::Always, JpLoc::ImmediateWord) => format!("JP {:#06X}", imm_word).into(),
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JP(cond, JpLoc::ImmediateWord) => format!("JP {:?} {:#06X}", cond, imm_word).into(),
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LD(LDTarget::IoWithC, LDSource::A) => "LD (0xFF00 + C), A".into(),
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LD(LDTarget::IndirectImmediateWord, LDSource::A) => {
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format!("LD ({:#06X}), A", imm_byte).into()
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}
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LD(LDTarget::A, LDSource::IoWithC) => "LD A, (0xFF00 + C)".into(),
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LD(LDTarget::A, LDSource::IndirectImmediateWord) => {
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format!("LD A, ({:#06X})", imm_word).into()
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}
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DI => "DI".into(),
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EI => "EI".into(),
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CALL(cond) => format!("CALL {:?} {:#06X}", cond, imm_word).into(),
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PUSH(rp) => format!("PUSH {:?}", rp).into(),
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ADD(AddTarget::A, AddSource::ImmediateByte) => {
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format!("ADD A, {:#04X}", imm_byte).into()
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}
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ADC(AluSource::ImmediateByte) => format!("ADC {:#04X}", imm_byte).into(),
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SUB(AluSource::ImmediateByte) => format!("SUB {:#04X}", imm_byte).into(),
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SBC(AluSource::ImmediateByte) => format!("SBC {:#04X}", imm_byte).into(),
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AND(AluSource::ImmediateByte) => format!("AND {:#04X}", imm_byte).into(),
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XOR(AluSource::ImmediateByte) => format!("XOR {:#04X}", imm_byte).into(),
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OR(AluSource::ImmediateByte) => format!("OR {:#04X}", imm_byte).into(),
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CP(AluSource::ImmediateByte) => format!("CP {:#04X}", imm_byte).into(),
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RST(v) => format!("RST {:#04X}", v).into(),
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_ => todo!(),
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// Prefixed Instructions
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RLC(reg) => format!("RLC {:?}", reg).into(),
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RRC(reg) => format!("RRC {:?}", reg).into(),
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RL(reg) => format!("RL {:?}", reg).into(),
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RR(reg) => format!("RR {:?}", reg).into(),
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SLA(reg) => format!("SLA {:?}", reg).into(),
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SRA(reg) => format!("SRA {:?}", reg).into(),
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SWAP(reg) => format!("SWAP {:?}", reg).into(),
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SRL(reg) => format!("SRL {:?}", reg).into(),
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BIT(bit, reg) => format!("BIT {}, {:?}", bit, reg).into(),
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RES(bit, reg) => format!("RES {}, {:?}", bit, reg).into(),
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SET(bit, reg) => format!("SET {}, {:?}", bit, reg).into(),
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_ => unreachable!("{:?} is an illegal instruction", instr),
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}
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}
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