src/bus.rs

@@ -247,7 +247,6 @@ impl BusIo for Bus {
                     0x49 => self.ppu.monochrome.obj_palette_1.into(),
                     0x4A => self.ppu.pos.window_y,
                     0x4B => self.ppu.pos.window_x,
-                    0x4D => 0xFF, // CGB Specific Register
                     _ => unimplemented!("Unable to read {:#06X} in I/O Registers", addr),
                 }
             }
@@ -377,7 +376,7 @@ impl BusIo for Bus {
                     0x49 => self.ppu.monochrome.obj_palette_1 = byte.into(),
                     0x4A => self.ppu.pos.window_y = byte,
                     0x4B => self.ppu.pos.window_x = byte,
-                    0x4D => {} // CGB Specific Register
+                    0x4D => {} // Writing to this address is useful on the CGB only
                     0x50 => {
                         // Disable Boot ROM
                         if byte != 0 {

src/cartridge.rs

@@ -157,18 +157,7 @@ impl Mbc1 {
         match self.bank_count {
             None | Four | Eight | Sixteen | ThirtyTwo => 0x00,
             SixtyFour => (self.ram_bank & 0x01) << 5,
-            OneHundredTwentyEight => (self.ram_bank & 0x03) << 5,
+            OneHundredTwentyEight => self.ram_bank << 5,
-            _ => unreachable!("{:?} is not a valid MBC1 BankCount", self.bank_count),
-        }
-    }
-
-    fn mbcm_zero_bank(&self) -> u8 {
-        use BankCount::*;
-
-        match self.bank_count {
-            None | Four | Eight | Sixteen | ThirtyTwo => 0x00,
-            SixtyFour => (self.ram_bank & 0x03) << 4,
-            OneHundredTwentyEight => (self.ram_bank & 0x03) << 5,
             _ => unreachable!("{:?} is not a valid MBC1 BankCount", self.bank_count),
         }
     }
@@ -176,39 +165,39 @@ impl Mbc1 {
     fn high_bank(&self) -> u8 {
         use BankCount::*;
 
-        let base = self.rom_bank & self.rom_size_mask();
+        let base = self.rom_bank & self.rom_bank_bitmask();
 
         match self.bank_count {
             None | Four | Eight | Sixteen | ThirtyTwo => base,
-            SixtyFour => base & !(0x01 << 5) | ((self.ram_bank & 0x01) << 5),
+            SixtyFour => (base & !(0x01 << 5)) | (self.ram_bank & 0x01) << 5,
-            OneHundredTwentyEight => base & !(0x03 << 5) | ((self.ram_bank & 0x03) << 5),
+            OneHundredTwentyEight => (base & !(0x03 << 5)) | (self.ram_bank & 0x03) << 5,
             _ => unreachable!("{:?} is not a valid MBC1 BankCount", self.bank_count),
         }
     }
 
-    fn rom_size_mask(&self) -> u8 {
+    fn rom_bank_bitmask(&self) -> u8 {
         use BankCount::*;
 
         match self.bank_count {
-            None => 0b00000001,
+            None => 0x1,
-            Four => 0b00000011,
+            Four => 0x03,
-            Eight => 0b00000111,
+            Eight => 0x07,
-            Sixteen => 0b00001111,
+            Sixteen => 0x0F,
-            ThirtyTwo | SixtyFour | OneHundredTwentyEight => 0b00011111,
+            ThirtyTwo | SixtyFour | OneHundredTwentyEight => 0x1F,
             _ => unreachable!("{:?} is not a valid MBC1 BankCount", self.bank_count),
         }
     }
 
-    fn ram_addr(&self, addr: u16) -> u16 {
+    fn ram_addr(&self, addr: u16) -> usize {
         use RamSize::*;
 
         match self.ram_size {
-            _2KB | _8KB => (addr - 0xA000) % self.ram_size.len() as u16,
+            _2KB | _8KB => (addr as usize - 0xA000) % self.ram_size.len() as usize,
             _32KB => {
                 if self.mode {
-                    0x2000 * self.ram_bank as u16 + (addr - 0xA000)
+                    0x2000 * self.ram_bank as usize + (addr as usize - 0xA000)
                 } else {
-                    addr - 0xA000
+                    addr as usize - 0xA000
                 }
             }
             _ => unreachable!("RAM size can not be greater than 32KB on MBC1"),
@@ -223,17 +212,19 @@ impl MemoryBankController for Mbc1 {
         match addr {
             0x0000..=0x3FFF => {
                 if self.mode {
-                    Address((0x4000 * self.zero_bank() as usize) + addr as usize)
+                    let zero_bank = self.zero_bank() as usize;
+                    Address(0x4000 * zero_bank + addr as usize)
                 } else {
                     Address(addr as usize)
                 }
             }
             0x4000..=0x7FFF => {
-                Address((0x4000 * self.high_bank() as usize) + (addr as usize - 0x4000))
+                let high_bank = self.high_bank() as usize;
+                Address(0x4000 * high_bank + (addr as usize - 0x4000))
             }
             0xA000..=0xBFFF => {
                 if self.ram_enabled {
-                    Value(self.ram[self.ram_addr(addr) as usize])
+                    Value(self.ram[self.ram_addr(addr)])
                 } else {
                     Value(0xFF)
                 }
@@ -249,18 +240,17 @@ impl MemoryBankController for Mbc1 {
                 self.rom_bank = if byte == 0x00 {
                     0x01
                 } else {
-                    byte & self.rom_size_mask()
+                    byte & self.rom_bank_bitmask()
-                };
+                }
-
-                self.rom_bank &= 0x1F;
             }
             0x4000..=0x5FFF => self.ram_bank = byte & 0x03,
             0x6000..=0x7FFF => self.mode = (byte & 0x01) == 0x01,
-            0xA000..=0xBFFF if self.ram_enabled => {
+            0xA000..=0xBFFF => {
-                let ram_addr = self.ram_addr(addr) as usize;
+                if self.ram_enabled {
+                    let ram_addr = self.ram_addr(addr);
                     self.ram[ram_addr] = byte;
                 }
-            0xA000..=0xBFFF => {} // Ram isn't enabled, ignored write
+            }
             _ => unreachable!("A write to {:#06X} should not be handled by MBC1", addr),
         }
     }
@@ -442,7 +432,7 @@ impl From<u8> for RamSize {
 
 #[derive(Debug, Clone, Copy)]
 enum BankCount {
-    None = 0x00,                  // 32KB (also called Two)
+    None = 0x00,                  // 32KB
     Four = 0x01,                  // 64KB
     Eight = 0x02,                 // 128KB
     Sixteen = 0x03,               // 256KB

src/sound.rs

@@ -58,7 +58,7 @@ impl Sound {
             // Check in this scope ensures (only) the above subtraction
             // made length_timer 0
             if self.ch1.length_timer == 0 {
-                self.ch1.enabled = false;
+                todo!("Disable Channel 1 until next trigger event");
             }
         }
 
@@ -68,7 +68,7 @@ impl Sound {
             // Check in this scope ensures (only) the above subtraction
             // made length_timer 0
             if self.ch2.length_timer == 0 {
-                self.ch2.enabled = false;
+                todo!("Disable Channel 2 until next trigger event");
             }
         }
 
@@ -78,7 +78,7 @@ impl Sound {
             // Check in this scope ensures (only) the above subtraction
             // made length_timer 0
             if self.ch3.length_timer == 0 {
-                self.ch3.enabled = false;
+                todo!("Disable Channel 3 until next trigger event");
             }
         }
 
@@ -88,7 +88,7 @@ impl Sound {
             // Check in this scope ensures (only) the above subtraction
             // made length_timer 0
             if self.ch4.length_timer == 0 {
-                self.ch4.enabled = false;
+                todo!("Disable Channel 4 until next trigger event");
             }
         }
     }
@@ -311,8 +311,6 @@ pub(crate) struct Channel1 {
 
     // Length Functionality
     length_timer: u16,
-
-    enabled: bool,
 }
 
 impl Channel1 {
@@ -376,7 +374,7 @@ impl Channel1 {
 
         // Overflow check
         if new_freq > 2047 {
-            self.enabled = false;
+            todo!("Frequency failed the overflow check. Disable the channel");
         }
 
         new_freq
@@ -466,8 +464,6 @@ pub(crate) struct Channel2 {
 
     // Length Functionality
     length_timer: u16,
-
-    enabled: bool,
 }
 
 impl Channel2 {
@@ -747,9 +743,7 @@ pub(crate) struct Channel4 {
     length_timer: u16,
 
     /// Linear Feedback Shift Register (15-bit)
-    shift_register: u16,
+    lfsr: u16,
-
-    enabled: bool,
 }
 
 impl Channel4 {
@@ -784,7 +778,7 @@ impl Channel4 {
             }
 
             // LFSR behaviour during trigger event
-            self.shift_register = 0x7FFF;
+            self.lfsr = 0x7FFF;
         }
     }
 }