src/cpu.rs

@@ -146,11 +146,11 @@ impl Cpu {
         self.handle_ei();
 
         // For use in Blargg's Test ROMs
-        // if self.read_byte(0xFF02) == 0x81 {
-        //     let c = self.read_byte(0xFF01) as char;
-        //     self.write_byte(0xFF02, 0x00);
-        //     eprint!("{}", c);
-        // }
+        if self.read_byte(0xFF02) == 0x81 {
+            let c = self.read_byte(0xFF01) as char;
+            self.write_byte(0xFF02, 0x00);
+            eprint!("{}", c);
+        }
 
         elapsed
     }

src/timer.rs

@@ -22,16 +22,29 @@ impl Timer {
         use TimerSpeed::*;
 
         match self.state {
-            TIMAOverflow(_) | AbortedTIMAOverflow(_) => self.next(),
+            TIMAOverflow(_) | AbortedTIMAOverflow(_) => self.state = self.state.next(),
             LoadTMA => {
                 self.counter = self.modulo;
                 self.interrupt = true;
 
-                self.next();
+                self.state.next();
             }
             Normal => {}
         }
 
+        if let TIMAOverflow(step) | AbortedTIMAOverflow(step) = self.state {
+            if step < 3 {
+                self.state = self.state.next();
+            } else {
+                if self.state == TIMAOverflow(step) {
+                    self.counter = self.modulo;
+                    self.interrupt = true;
+                }
+
+                self.state = Normal;
+            }
+        }
+
         self.divider = self.divider.wrapping_add(1);
 
         // Get Bit Position
@@ -90,18 +103,6 @@ impl Timer {
             self.state = State::TIMAOverflow(0);
         }
     }
-
-    fn next(&mut self) {
-        use State::*;
-
-        self.state = match self.state {
-            Normal | LoadTMA => Normal,
-            AbortedTIMAOverflow(4) => Normal,
-            TIMAOverflow(4) => LoadTMA,
-            AbortedTIMAOverflow(step) => AbortedTIMAOverflow(step + 1),
-            TIMAOverflow(step) => TIMAOverflow(step + 1),
-        }
-    }
 }
 
 impl Default for Timer {
@@ -183,3 +184,17 @@ enum State {
     Normal,
     LoadTMA,
 }
+
+impl State {
+    fn next(&self) -> Self {
+        use State::*;
+
+        match self {
+            Normal | LoadTMA => Normal,
+            TIMAOverflow(3) => LoadTMA,
+            AbortedTIMAOverflow(3) => Normal,
+            TIMAOverflow(step) => TIMAOverflow(step + 1),
+            AbortedTIMAOverflow(step) => AbortedTIMAOverflow(step + 1),
+        }
+    }
+}