chore: refactor LDTarget and InstrRegister
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2e1c97e5d7
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db86d11085
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@ -72,6 +72,7 @@ pub enum MATHTarget {
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#[derive(Debug, Copy, Clone)]
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pub enum LDTarget {
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IndirectC,
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Register(InstrRegister),
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IndirectRegister(InstrRegisterPair),
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ByteAtAddress(u16),
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@ -103,6 +104,18 @@ enum InstrRegister {
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H,
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L,
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IndirectHL, // (HL)
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}
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#[derive(Debug, Clone, Copy)]
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enum InstrRegisterWithC {
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A,
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B,
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C,
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D,
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E,
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H,
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L,
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IndirectHL, // (HL)
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IndirectC, // (0xFF00 + C)
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}
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@ -215,22 +228,15 @@ impl Instruction {
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cpu.set_register(Register::try_from(reg).unwrap(), n);
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Cycles(8)
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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}
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(
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LDTarget::Register(InstrRegister::IndirectC),
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LDTarget::Register(InstrRegister::A),
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) => {
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(LDTarget::IndirectC, LDTarget::Register(InstrRegister::A)) => {
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// LD (0xFF00 + C), A | Store value of register A at address 0xFF00 + C
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let addr = 0xFF00 + cpu.register(Register::C) as u16;
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cpu.write_byte(addr, cpu.register(Register::A));
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Cycles(8)
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}
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(
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LDTarget::Register(InstrRegister::A),
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LDTarget::Register(InstrRegister::IndirectC),
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) => {
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(LDTarget::Register(InstrRegister::A), LDTarget::IndirectC) => {
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let addr = 0xFF00 + cpu.register(Register::C) as u16;
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cpu.set_register(Register::A, cpu.read_byte(addr));
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Cycles(8)
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@ -359,7 +365,6 @@ impl Instruction {
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sum = Self::add_u8s(a_value, value, &mut flags);
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cycles = Cycles(4);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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cpu.set_register(Register::A, sum);
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@ -414,7 +419,6 @@ impl Instruction {
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);
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cycles = Cycles(12)
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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cpu.set_register(Register::Flag, flags.into());
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cycles
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@ -470,7 +474,6 @@ impl Instruction {
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cpu.write_byte(addr, Self::dec_register(cpu.read_byte(addr), &mut flags));
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cycles = Cycles(12);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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cpu.set_register(Register::Flag, flags.into());
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cycles
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@ -588,7 +591,6 @@ impl Instruction {
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sum = Self::add_u8s(a_value, value, &mut flags);
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cycles = Cycles(8);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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cpu.set_register(Register::Flag, flags.into());
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cpu.set_register(Register::A, sum);
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@ -631,7 +633,6 @@ impl Instruction {
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diff = Self::sub_u8s(a_value, value, &mut flags);
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cycles = Cycles(8);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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cpu.set_register(Register::Flag, flags.into());
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@ -676,7 +677,6 @@ impl Instruction {
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diff = Self::sub_u8s(a_value, value, &mut flags);
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cycles = Cycles(8);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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cpu.set_register(Register::A, diff);
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@ -721,7 +721,6 @@ impl Instruction {
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result = a_value & value;
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cycles = Cycles(8);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(result == 0, false, true, false);
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@ -766,7 +765,6 @@ impl Instruction {
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result = a_value ^ value;
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cycles = Cycles(8);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(result == 0, false, false, false);
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@ -811,7 +809,6 @@ impl Instruction {
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result = a_value | value;
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cycles = Cycles(8);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(result == 0, false, false, false);
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@ -855,7 +852,6 @@ impl Instruction {
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let _ = Self::sub_u8s(a_value, value, &mut flags);
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cycles = Cycles(8);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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cpu.set_register(Register::Flag, flags.into());
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@ -1099,7 +1095,6 @@ impl Instruction {
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cpu.write_byte(addr, rot_reg);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(rot_reg == 0, false, false, msb == 0x01);
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@ -1140,7 +1135,6 @@ impl Instruction {
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cpu.write_byte(addr, rot_reg);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(rot_reg == 0, false, false, lsb == 0x01);
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@ -1183,7 +1177,6 @@ impl Instruction {
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cpu.write_byte(addr, rot_reg);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(rot_reg == 0, false, false, carry);
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@ -1227,7 +1220,6 @@ impl Instruction {
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cpu.write_byte(addr, rot_reg);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(rot_reg == 0, false, false, carry);
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@ -1269,7 +1261,6 @@ impl Instruction {
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cpu.write_byte(addr, value);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unimplemented!(),
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}
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flags.update(shift_reg == 0, false, false, msb == 0x01);
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@ -1313,7 +1304,6 @@ impl Instruction {
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cpu.write_byte(addr, value);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unimplemented!(),
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}
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flags.update(shift_reg == 0, false, false, lsb == 0x01);
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@ -1353,7 +1343,6 @@ impl Instruction {
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cpu.write_byte(addr, swap_reg);
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cycles = Cycles(16)
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(swap_reg == 0, false, false, false);
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@ -1395,7 +1384,6 @@ impl Instruction {
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cpu.write_byte(addr, shift_reg);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(shift_reg == 0, false, false, lsb == 0x01);
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@ -1429,7 +1417,6 @@ impl Instruction {
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is_bit_set = ((value >> y) & 0x01) == 0x01;
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cycles = Cycles(12);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(!is_bit_set, false, true, flags.c);
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@ -1464,7 +1451,6 @@ impl Instruction {
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cpu.write_byte(addr, value & !(1u8 << y));
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Cycles(16)
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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}
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Instruction::SET(y, reg) => {
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@ -1493,7 +1479,6 @@ impl Instruction {
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cpu.write_byte(addr, value | (1u8 << y));
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Cycles(16)
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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}
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}
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@ -1786,7 +1771,7 @@ impl Instruction {
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),
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(3, 2, _, 4, _) => Self::LD(
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// LD (0xFF00 + C) ,A
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LDTarget::Register(InstrRegister::IndirectC),
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LDTarget::IndirectC,
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LDTarget::Register(InstrRegister::A),
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),
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(3, 2, _, 5, _) => Self::LD(
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@ -1797,7 +1782,7 @@ impl Instruction {
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(3, 2, _, 6, _) => Self::LD(
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// LD A, (0xFF00 + C)
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LDTarget::Register(InstrRegister::A),
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LDTarget::Register(InstrRegister::IndirectC),
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LDTarget::IndirectC,
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),
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(3, 2, _, 7, _) => Self::LD(
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// LD A, (nn)
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@ -1919,9 +1904,6 @@ impl TryFrom<InstrRegister> for Register {
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InstrRegister::IndirectHL => {
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Err("Can not convert InstrRegister::IndirectHL to Register".to_string())
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}
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InstrRegister::IndirectC => {
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Err("Can not convert InstrRegister::IndirectC to Register".to_string())
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}
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}
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}
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}
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