Implement Instructions and rename enums
This commit is contained in:
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0be0030ed7
commit
cb365fd932
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@ -57,7 +57,7 @@ impl Cpu {
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Register::E => self.reg.e = value,
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Register::H => self.reg.h = value,
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Register::L => self.reg.l = value,
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Register::Flags => self.reg.a = value.into(),
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Register::Flag => self.reg.a = value.into(),
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}
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}
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@ -70,7 +70,7 @@ impl Cpu {
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Register::E => self.reg.e,
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Register::H => self.reg.h,
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Register::L => self.reg.l,
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Register::Flags => self.flags.into(),
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Register::Flag => self.flags.into(),
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}
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}
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@ -120,7 +120,7 @@ pub enum Register {
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E,
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H,
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L,
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Flags,
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Flag,
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}
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pub enum RegisterPair {
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@ -5,8 +5,8 @@ pub enum Instruction {
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STOP,
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JR(JumpCondition, i8),
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ADD(MATHTarget, MATHTarget),
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INC(AllRegisters),
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DEC(AllRegisters),
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INC(Registers),
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DEC(Registers),
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RLCA,
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RRCA,
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RLA,
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@ -58,28 +58,28 @@ impl Instruction {
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}
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Cycles(12)
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}
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(LDTarget::IndirectRegister(pair), LDTarget::Register(InstrRegisters::A)) => {
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(LDTarget::IndirectRegister(pair), LDTarget::Register(InstrRegister::A)) => {
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let a = cpu.register(Register::A);
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match pair {
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InstrRegisterPairs::BC => {
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InstrRegisterPair::BC => {
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// LD (BC), A | Put A into memory address BC
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let addr = cpu.register_pair(RegisterPair::BC);
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cpu.write_byte(addr, a);
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}
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InstrRegisterPairs::DE => {
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InstrRegisterPair::DE => {
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// LD (DE), A | Put A into memory address DE
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let addr = cpu.register_pair(RegisterPair::DE);
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cpu.write_byte(addr, a);
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}
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InstrRegisterPairs::IncrementHL => {
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InstrRegisterPair::IncrementHL => {
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// LD (HL+), A | Put A into memory address HL, then increment HL
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let addr = cpu.register_pair(RegisterPair::HL);
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cpu.write_byte(addr, a);
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cpu.set_register_pair(RegisterPair::HL, addr + 1);
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}
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InstrRegisterPairs::DecrementHL => {
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InstrRegisterPair::DecrementHL => {
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// LD (HL-), A | Put A into memory address HL, then decrement HL
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let addr = cpu.register_pair(RegisterPair::HL);
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cpu.write_byte(addr, a);
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@ -90,26 +90,26 @@ impl Instruction {
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}
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Cycles(8)
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}
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(LDTarget::Register(InstrRegisters::A), LDTarget::IndirectRegister(pair)) => {
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(LDTarget::Register(InstrRegister::A), LDTarget::IndirectRegister(pair)) => {
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match pair {
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InstrRegisterPairs::BC => {
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InstrRegisterPair::BC => {
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// LD A, (BC) | Put value at address BC into A
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let addr = cpu.register_pair(RegisterPair::BC);
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cpu.set_register(Register::A, cpu.read_byte(addr));
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}
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InstrRegisterPairs::DE => {
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InstrRegisterPair::DE => {
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// LD A, (DE) | Put value at address DE into A
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let addr = cpu.register_pair(RegisterPair::DE);
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cpu.set_register(Register::A, cpu.read_byte(addr));
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}
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InstrRegisterPairs::IncrementHL => {
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InstrRegisterPair::IncrementHL => {
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// LD A, (HL+) | Put value at address HL into A, then increment HL
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let addr = cpu.register_pair(RegisterPair::HL);
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cpu.set_register(Register::A, cpu.read_byte(addr));
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cpu.set_register_pair(RegisterPair::HL, addr + 1);
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}
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InstrRegisterPairs::DecrementHL => {
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InstrRegisterPair::DecrementHL => {
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// LD A, (HL-) | Put value at address HL into A, then increment HL
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let addr = cpu.register_pair(RegisterPair::HL);
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cpu.set_register(Register::A, cpu.read_byte(addr));
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@ -125,40 +125,40 @@ impl Instruction {
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let cycles: Cycles;
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match reg {
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InstrRegisters::B => {
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InstrRegister::B => {
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cpu.set_register(Register::B, n);
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cycles = Cycles(8);
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}
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InstrRegisters::C => {
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InstrRegister::C => {
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cpu.set_register(Register::C, n);
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cycles = Cycles(8);
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}
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InstrRegisters::D => {
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InstrRegister::D => {
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cpu.set_register(Register::D, n);
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cycles = Cycles(8);
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}
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InstrRegisters::E => {
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InstrRegister::E => {
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cpu.set_register(Register::E, n);
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cycles = Cycles(8);
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}
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InstrRegisters::H => {
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InstrRegister::H => {
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cpu.set_register(Register::H, n);
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cycles = Cycles(8);
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}
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InstrRegisters::L => {
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InstrRegister::L => {
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cpu.set_register(Register::L, n);
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cycles = Cycles(8);
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}
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InstrRegisters::IndirectHL => {
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InstrRegister::IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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cpu.write_byte(addr, n);
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cycles = Cycles(12);
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}
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InstrRegisters::A => {
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InstrRegister::A => {
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cpu.set_register(Register::A, n);
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cycles = Cycles(8);
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}
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InstrRegisters::IndirectC => unreachable!(),
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InstrRegister::IndirectC => unreachable!(),
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}
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cycles
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}
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@ -169,7 +169,7 @@ impl Instruction {
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// JR cc[y - 4], d | If condition is true, then add d to current address and jump
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// JR d | Add d to current address and jump
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let prev = cpu.register_pair(RegisterPair::PC);
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let flags: Flags = cpu.register(Register::Flags).into();
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let flags: Flags = cpu.register(Register::Flag).into();
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let new_address = (prev as i16 + offset as i16) as u16;
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match cond {
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@ -212,7 +212,7 @@ impl Instruction {
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(MATHTarget::RegisterPair(RegisterPair::HL), MATHTarget::RegisterPair(pair)) => {
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// ADD HL, rp[p] | add register pair to HL.
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let hl = cpu.register_pair(RegisterPair::HL);
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let mut flags: Flags = cpu.register(Register::Flags).into();
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let sum;
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match pair {
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@ -233,13 +233,13 @@ impl Instruction {
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}
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_ => unreachable!(),
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}
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cpu.set_register(Register::Flags, flags.into());
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cpu.set_register(Register::Flag, flags.into());
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cpu.set_register_pair(RegisterPair::HL, sum);
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Cycles(8)
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}
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_ => unimplemented!(),
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},
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Instruction::INC(AllRegisters::Word(pair)) => {
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Instruction::INC(Registers::Word(pair)) => {
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// INC rp[p] | Increment Register Pair
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match pair {
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RegisterPair::BC => {
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@ -262,58 +262,58 @@ impl Instruction {
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}
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Cycles(8)
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}
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Instruction::INC(AllRegisters::Byte(reg)) => {
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Instruction::INC(Registers::Byte(reg)) => {
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// INC r[y] | Increment Register
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let mut flags: Flags = cpu.register(Register::Flags).into();
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let cycles: Cycles;
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match reg {
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InstrRegisters::B => {
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InstrRegister::B => {
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let b = cpu.register(Register::B);
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cpu.set_register(Register::B, Self::inc_register(b, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::C => {
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InstrRegister::C => {
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let c = cpu.register(Register::C);
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cpu.set_register(Register::C, Self::inc_register(c, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::D => {
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InstrRegister::D => {
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let d = cpu.register(Register::D);
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cpu.set_register(Register::D, Self::inc_register(d, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::E => {
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InstrRegister::E => {
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let e = cpu.register(Register::E);
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cpu.set_register(Register::E, Self::inc_register(e, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::H => {
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InstrRegister::H => {
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let h = cpu.register(Register::H);
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cpu.set_register(Register::H, Self::inc_register(h, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::L => {
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InstrRegister::L => {
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let l = cpu.register(Register::L);
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cpu.set_register(Register::L, Self::inc_register(l, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::IndirectHL => {
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InstrRegister::IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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cpu.write_byte(addr, Self::inc_register(cpu.read_byte(addr), &mut flags));
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cycles = Cycles(12);
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}
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InstrRegisters::A => {
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InstrRegister::A => {
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let a = cpu.register(Register::A);
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cpu.set_register(Register::A, Self::inc_register(a, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::IndirectC => unreachable!(),
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InstrRegister::IndirectC => unreachable!(),
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}
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cpu.set_register(Register::Flags, flags.into());
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cpu.set_register(Register::Flag, flags.into());
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cycles
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}
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Instruction::DEC(AllRegisters::Word(pair)) => {
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Instruction::DEC(Registers::Word(pair)) => {
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// DEC rp[p] | Decrement Register Pair
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match pair {
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RegisterPair::BC => {
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@ -336,89 +336,154 @@ impl Instruction {
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}
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Cycles(8)
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}
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Instruction::DEC(AllRegisters::Byte(reg)) => {
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Instruction::DEC(Registers::Byte(reg)) => {
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// DEC r[y] | Decrement Register
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let mut flags: Flags = cpu.register(Register::Flags).into();
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let cycles: Cycles;
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match reg {
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InstrRegisters::B => {
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InstrRegister::B => {
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let b = cpu.register(Register::B);
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cpu.set_register(Register::B, Self::dec_register(b, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::C => {
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InstrRegister::C => {
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let c = cpu.register(Register::C);
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cpu.set_register(Register::C, Self::dec_register(c, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::D => {
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InstrRegister::D => {
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let d = cpu.register(Register::D);
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cpu.set_register(Register::D, Self::dec_register(d, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::E => {
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InstrRegister::E => {
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let e = cpu.register(Register::E);
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cpu.set_register(Register::E, Self::dec_register(e, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::H => {
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InstrRegister::H => {
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let h = cpu.register(Register::H);
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cpu.set_register(Register::H, Self::dec_register(h, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::L => {
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InstrRegister::L => {
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let l = cpu.register(Register::L);
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cpu.set_register(Register::L, Self::dec_register(l, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::IndirectHL => {
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InstrRegister::IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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cpu.write_byte(addr, Self::dec_register(cpu.read_byte(addr), &mut flags));
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cycles = Cycles(12);
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}
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InstrRegisters::A => {
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InstrRegister::A => {
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let a = cpu.register(Register::A);
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cpu.set_register(Register::A, Self::dec_register(a, &mut flags));
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cycles = Cycles(4);
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}
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InstrRegisters::IndirectC => unreachable!(),
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InstrRegister::IndirectC => unreachable!(),
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}
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cpu.set_register(Register::Flags, flags.into());
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cpu.set_register(Register::Flag, flags.into());
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cycles
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}
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Instruction::RLCA => {
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// FIXME: Pretty sure this is an incorrect implementation
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let mut flags: Flags = cpu.register(Register::Flags).into();
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let a = cpu.register(Register::A);
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let carry_bit = (a & 0x80) >> 7;
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let new_a = a << 1;
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let cache = a >> 7; // get the 7th bit (this will be the carry bit + the one that is wrapped around)
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let rot_a = (a << 1) | (cache << 0); // (rotate a left), then set the first bit (which will be a 0 by default)
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flags.z = 0 == new_a;
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flags.z = false;
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flags.n = false;
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flags.h = false;
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flags.c = carry_bit == 0x01;
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flags.c = cache == 0x01;
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cpu.set_register(Register::A, new_a);
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cpu.set_register(Register::Flag, flags.into());
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cpu.set_register(Register::A, rot_a);
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Cycles(4)
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}
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Instruction::RRCA => {
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// FIXME: Pretty sure this is an incorrect implementation
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let mut flags: Flags = cpu.register(Register::Flags).into();
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let a = cpu.register(Register::A);
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let carry_bit = a & 0x01;
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let new_a = a >> 1;
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let cache = a & 0x01; // RLCA but the other way around
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let rot_a = (a >> 1) | (cache << 7);
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flags.z = new_a == 0;
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flags.z = false;
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flags.n = false;
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flags.h = false;
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flags.c = carry_bit == 0x01;
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flags.c = cache == 0x01;
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cpu.set_register(Register::A, new_a);
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cpu.set_register(Register::Flag, flags.into());
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cpu.set_register(Register::A, rot_a);
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Cycles(4)
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}
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Instruction::RLA => {
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let a = cpu.register(Register::A);
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let cache = a >> 7;
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let rot_a = (a << 1) | ((flags.c as u8) << 0);
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flags.z = false;
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flags.n = false;
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flags.h = false;
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flags.c = cache == 0x01;
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cpu.set_register(Register::Flag, flags.into());
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cpu.set_register(Register::A, rot_a);
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Cycles(4)
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}
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Instruction::RRA => {
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let a = cpu.register(Register::A);
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let cache = a & 0x01;
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let rot_a = (a >> 1) | ((flags.c as u8) << 7);
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flags.z = false;
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flags.n = false;
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flags.h = false;
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flags.c = cache == 0x01;
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cpu.set_register(Register::Flag, flags.into());
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cpu.set_register(Register::A, rot_a);
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Cycles(4)
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}
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Instruction::DAA => unimplemented!(),
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Instruction::CPL => {
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let a = cpu.register(Register::A);
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flags.n = true;
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flags.h = true;
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cpu.set_register(Register::Flag, flags.into());
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cpu.set_register(Register::A, !a); // Bitwise not is ! instead of ~
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Cycles(4)
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}
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Instruction::SCF => {
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let mut flags: Flags = cpu.register(Register::Flag).into();
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flags.n = false;
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flags.h = false;
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flags.c = true;
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cpu.set_register(Register::Flag, flags.into());
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Cycles(4)
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}
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Instruction::CCF => {
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let mut flags: Flags = cpu.register(Register::Flag).into();
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flags.n = false;
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flags.h = false;
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flags.c = !flags.c;
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cpu.set_register(Register::Flag, flags.into());
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Cycles(4)
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}
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_ => unimplemented!(),
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}
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}
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@ -503,59 +568,59 @@ impl Instruction {
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),
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(0, 2, 0, _, 0) => Instruction::LD(
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// LD (BC), A
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LDTarget::IndirectRegister(InstrRegisterPairs::BC),
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LDTarget::Register(InstrRegisters::A),
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LDTarget::IndirectRegister(InstrRegisterPair::BC),
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LDTarget::Register(InstrRegister::A),
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),
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(0, 2, 0, _, 1) => Instruction::LD(
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// LD (DE), A
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LDTarget::IndirectRegister(InstrRegisterPairs::DE),
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LDTarget::Register(InstrRegisters::A),
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LDTarget::IndirectRegister(InstrRegisterPair::DE),
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LDTarget::Register(InstrRegister::A),
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),
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(0, 2, 1, _, 0) => Instruction::LD(
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// LD A, (BC)
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LDTarget::Register(InstrRegisters::A),
|
||||
LDTarget::IndirectRegister(InstrRegisterPairs::BC),
|
||||
LDTarget::Register(InstrRegister::A),
|
||||
LDTarget::IndirectRegister(InstrRegisterPair::BC),
|
||||
),
|
||||
(0, 2, 1, _, 1) => Instruction::LD(
|
||||
// LD A, (DE)
|
||||
LDTarget::Register(InstrRegisters::A),
|
||||
LDTarget::IndirectRegister(InstrRegisterPairs::DE),
|
||||
LDTarget::Register(InstrRegister::A),
|
||||
LDTarget::IndirectRegister(InstrRegisterPair::DE),
|
||||
),
|
||||
(0, 2, 0, _, 2) => Instruction::LD(
|
||||
// LD (HL+), A
|
||||
LDTarget::IndirectRegister(InstrRegisterPairs::IncrementHL),
|
||||
LDTarget::Register(InstrRegisters::A),
|
||||
LDTarget::IndirectRegister(InstrRegisterPair::IncrementHL),
|
||||
LDTarget::Register(InstrRegister::A),
|
||||
),
|
||||
(0, 2, 0, _, 3) => Instruction::LD(
|
||||
// LD (HL-), A
|
||||
LDTarget::IndirectRegister(InstrRegisterPairs::DecrementHL),
|
||||
LDTarget::Register(InstrRegisters::A),
|
||||
LDTarget::IndirectRegister(InstrRegisterPair::DecrementHL),
|
||||
LDTarget::Register(InstrRegister::A),
|
||||
),
|
||||
(0, 2, 1, _, 2) => Instruction::LD(
|
||||
// LD A, (HL+)
|
||||
LDTarget::Register(InstrRegisters::A),
|
||||
LDTarget::IndirectRegister(InstrRegisterPairs::IncrementHL),
|
||||
LDTarget::Register(InstrRegister::A),
|
||||
LDTarget::IndirectRegister(InstrRegisterPair::IncrementHL),
|
||||
),
|
||||
(0, 2, 1, _, 3) => Instruction::LD(
|
||||
// LD A, (HL-)
|
||||
LDTarget::Register(InstrRegisters::A),
|
||||
LDTarget::IndirectRegister(InstrRegisterPairs::DecrementHL),
|
||||
LDTarget::Register(InstrRegister::A),
|
||||
LDTarget::IndirectRegister(InstrRegisterPair::DecrementHL),
|
||||
),
|
||||
(0, 3, 0, _, _) => Instruction::INC(
|
||||
// INC rp[p]
|
||||
AllRegisters::Word(Table::rp(p)),
|
||||
Registers::Word(Table::rp(p)),
|
||||
),
|
||||
(0, 3, 1, _, _) => Instruction::DEC(
|
||||
// DEC rp[p]
|
||||
AllRegisters::Word(Table::rp(p)),
|
||||
Registers::Word(Table::rp(p)),
|
||||
),
|
||||
(0, 4, _, _, _) => Instruction::INC(
|
||||
// INC r[y]
|
||||
AllRegisters::Byte(Table::r(y)),
|
||||
Registers::Byte(Table::r(y)),
|
||||
),
|
||||
(0, 5, _, _, _) => Instruction::DEC(
|
||||
// DEC r[y]
|
||||
AllRegisters::Byte(Table::r(y)),
|
||||
Registers::Byte(Table::r(y)),
|
||||
),
|
||||
(0, 6, _, _, _) => Instruction::LD(
|
||||
// LD r[y], n
|
||||
|
|
@ -581,7 +646,7 @@ impl Instruction {
|
|||
(3, 0, _, 4, _) => Instruction::LD(
|
||||
// LD (0xFF00 + n), A
|
||||
LDTarget::ByteAtAddress(0xFF00 + (n as u16)), // TODO: Do we want to do any calculations here?
|
||||
LDTarget::Register(InstrRegisters::A),
|
||||
LDTarget::Register(InstrRegister::A),
|
||||
),
|
||||
(3, 0, _, 5, _) => Instruction::ADD(
|
||||
// ADD SP, d
|
||||
|
|
@ -590,7 +655,7 @@ impl Instruction {
|
|||
),
|
||||
(3, 0, _, 6, _) => Instruction::LD(
|
||||
// LD A, (0xFF00 + n)
|
||||
LDTarget::Register(InstrRegisters::A),
|
||||
LDTarget::Register(InstrRegister::A),
|
||||
LDTarget::ByteAtAddress(0xFF00 + (n as u16)), // TODO: DO we want to do any calculations here?
|
||||
),
|
||||
(3, 0, _, 7, _) => Instruction::LDHL(n as i8), // LD HL, SP + d
|
||||
|
|
@ -614,22 +679,22 @@ impl Instruction {
|
|||
),
|
||||
(3, 2, _, 4, _) => Instruction::LD(
|
||||
// LD (0xFF00 + C) ,A
|
||||
LDTarget::Register(InstrRegisters::IndirectC),
|
||||
LDTarget::Register(InstrRegisters::A),
|
||||
LDTarget::Register(InstrRegister::IndirectC),
|
||||
LDTarget::Register(InstrRegister::A),
|
||||
),
|
||||
(3, 2, _, 5, _) => Instruction::LD(
|
||||
// LD (nn), A
|
||||
LDTarget::ByteAtAddress(nn),
|
||||
LDTarget::Register(InstrRegisters::A),
|
||||
LDTarget::Register(InstrRegister::A),
|
||||
),
|
||||
(3, 2, _, 6, _) => Instruction::LD(
|
||||
// LD A, (0xFF00 + C)
|
||||
LDTarget::Register(InstrRegisters::A),
|
||||
LDTarget::Register(InstrRegisters::IndirectC),
|
||||
LDTarget::Register(InstrRegister::A),
|
||||
LDTarget::Register(InstrRegister::IndirectC),
|
||||
),
|
||||
(3, 2, _, 7, _) => Instruction::LD(
|
||||
// LD A, (nn)
|
||||
LDTarget::Register(InstrRegisters::A),
|
||||
LDTarget::Register(InstrRegister::A),
|
||||
LDTarget::ByteAtAddress(nn),
|
||||
),
|
||||
(3, 3, _, 0, _) => Instruction::JP(
|
||||
|
|
@ -672,29 +737,29 @@ pub enum JPTarget {
|
|||
ImmediateWord(u16),
|
||||
}
|
||||
|
||||
pub enum AllRegisters {
|
||||
Byte(InstrRegisters),
|
||||
pub enum Registers {
|
||||
Byte(InstrRegister),
|
||||
Word(RegisterPair),
|
||||
}
|
||||
|
||||
pub enum MATHTarget {
|
||||
HL,
|
||||
SP,
|
||||
Register(InstrRegisters),
|
||||
Register(InstrRegister),
|
||||
RegisterPair(RegisterPair),
|
||||
ImmediateByte(u8),
|
||||
}
|
||||
|
||||
pub enum LDTarget {
|
||||
Register(InstrRegisters),
|
||||
IndirectRegister(InstrRegisterPairs),
|
||||
Register(InstrRegister),
|
||||
IndirectRegister(InstrRegisterPair),
|
||||
ByteAtAddress(u16),
|
||||
ImmediateWord(u16),
|
||||
ImmediateByte(u8),
|
||||
RegisterPair(RegisterPair),
|
||||
}
|
||||
|
||||
enum InstrRegisterPairs {
|
||||
enum InstrRegisterPair {
|
||||
AF,
|
||||
BC,
|
||||
DE,
|
||||
|
|
@ -705,7 +770,7 @@ enum InstrRegisterPairs {
|
|||
DecrementHL,
|
||||
}
|
||||
|
||||
enum InstrRegisters {
|
||||
enum InstrRegister {
|
||||
A,
|
||||
B,
|
||||
C,
|
||||
|
|
@ -728,16 +793,16 @@ pub enum JumpCondition {
|
|||
struct Table;
|
||||
|
||||
impl Table {
|
||||
pub fn r(index: u8) -> InstrRegisters {
|
||||
pub fn r(index: u8) -> InstrRegister {
|
||||
match index {
|
||||
0 => InstrRegisters::B,
|
||||
1 => InstrRegisters::C,
|
||||
2 => InstrRegisters::D,
|
||||
3 => InstrRegisters::E,
|
||||
4 => InstrRegisters::H,
|
||||
5 => InstrRegisters::L,
|
||||
6 => InstrRegisters::IndirectHL,
|
||||
7 => InstrRegisters::A,
|
||||
0 => InstrRegister::B,
|
||||
1 => InstrRegister::C,
|
||||
2 => InstrRegister::D,
|
||||
3 => InstrRegister::E,
|
||||
4 => InstrRegister::H,
|
||||
5 => InstrRegister::L,
|
||||
6 => InstrRegister::IndirectHL,
|
||||
7 => InstrRegister::A,
|
||||
_ => unreachable!("Index {} is out of bounds in r[]", index),
|
||||
}
|
||||
}
|
||||
|
|
@ -776,18 +841,18 @@ impl Table {
|
|||
match fn_index {
|
||||
0 => Instruction::ADD(
|
||||
// ADD A, r[z]
|
||||
MATHTarget::Register(InstrRegisters::A),
|
||||
MATHTarget::Register(InstrRegister::A),
|
||||
MATHTarget::Register(Self::r(r_index)),
|
||||
),
|
||||
1 => Instruction::ADC(
|
||||
// ADC A, r[z]
|
||||
MATHTarget::Register(InstrRegisters::A),
|
||||
MATHTarget::Register(InstrRegister::A),
|
||||
MATHTarget::Register(Self::r(r_index)),
|
||||
),
|
||||
2 => Instruction::SUB(MATHTarget::Register(Self::r(r_index))), // SUB r[z]
|
||||
3 => Instruction::SBC(
|
||||
// SBC A, r[z]
|
||||
MATHTarget::Register(InstrRegisters::A),
|
||||
MATHTarget::Register(InstrRegister::A),
|
||||
MATHTarget::Register(Self::r(r_index)),
|
||||
),
|
||||
4 => Instruction::AND(MATHTarget::Register(Self::r(r_index))), // AND r[z]
|
||||
|
|
|
|||
Loading…
Reference in New Issue