Restart Project
This commit is contained in:
Rekai Musuka
parent
a3cd9166ab
commit
b274d61f56
12
src/bus.rs
12
src/bus.rs
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@ -1,12 +0,0 @@
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#[derive(Debug, Copy, Clone)]
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pub struct MemoryBus {}
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impl MemoryBus {
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pub fn read_byte(&self, _address: u16) -> u8 {
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unimplemented!()
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}
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pub fn write_byte(&self, _address: u16) {
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unimplemented!()
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}
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}
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239
src/cpu.rs
239
src/cpu.rs
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@ -1,239 +0,0 @@
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use super::bus::MemoryBus;
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use std::convert::From;
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use std::ops::{Index, IndexMut};
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#[derive(Debug, Copy, Clone)]
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pub struct LR35902 {
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bus: MemoryBus,
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registers: Registers,
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sp: u16, // Stack Pointer
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pc: u16, // Program Counter
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ime: bool, // Interrupt Master Enable Flag
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}
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impl LR35902 {
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pub fn fetch() -> u8 {
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unimplemented!()
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}
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fn decode(opcode: u8) -> Instruction {
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unimplemented!()
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}
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fn execute(&mut self, instruction: Instruction) {
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match instruction {
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Instruction::Add(target, source) => {
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match target {
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Argument::Register(reg) => {
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let right = match source {
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Argument::Register(other) => self.registers[other], // ADD A, r
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Argument::ImmediateByte(byte) => byte, // ADD A, n
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Argument::IndirectRegisterPair(pair) => {
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// ADD A, (HL)
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self.bus.read_byte(self.register_pair(pair))
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}
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_ => unreachable!(),
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};
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self.registers[reg] = self.add(self.registers[reg], right);
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}
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Argument::RegisterPair(pair) => {
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let left = self.register_pair(pair);
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if let Argument::RegisterPair(other) = source {
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// ADD HL, rr
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let sum = self.add_u16(left, self.register_pair(other));
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self.set_register_pair(pair, sum);
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} else if let Argument::ImmediateByte(byte) = source {
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// ADD SP, dd
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let byte = byte as i8;
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let sum = self.add_u16_i8(left, byte);
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self.set_register_pair(pair, sum);
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}
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}
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_ => unreachable!(),
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}
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}
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_ => unimplemented!("Unhandled Instruction {:?}", instruction),
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}
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}
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fn add_u16_i8(&mut self, left: u16, right: i8) -> u16 {
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unimplemented!()
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}
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fn add_u16(&mut self, left: u16, right: u16) -> u16 {
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unimplemented!()
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}
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fn add(&mut self, left: u8, right: u8) -> u8 {
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// Info on the Half-Carry flag
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// https://robdor.com/2016/08/10/gameboy-emulator-half-carry-flag/
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let (res, did_overflow) = left.overflowing_add(right);
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self.registers.f = Flag {
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z: res == 0,
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n: false,
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h: (((left & 0x0F) + (right & 0x0F)) & 0x10) == 0x10,
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c: did_overflow,
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}
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.into();
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res
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}
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}
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#[derive(Debug, Copy, Clone)]
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pub struct Flag {
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z: bool, // Zero Flag
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n: bool, // Subtract Flag
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h: bool, // Half-Carry Flag
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c: bool, // Carry Flag
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}
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impl From<u8> for Flag {
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fn from(num: u8) -> Self {
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Flag {
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z: (num >> 7) == 1,
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n: ((num >> 6) & 0x01) == 1,
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h: ((num >> 5) & 0x01) == 1,
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c: ((num >> 4) & 0x01) == 1,
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}
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}
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}
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impl From<Flag> for u8 {
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fn from(flag: Flag) -> Self {
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(flag.z as u8) << 7 | (flag.n as u8) << 6 | (flag.h as u8) << 5 | (flag.c as u8) << 4
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}
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}
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#[derive(Debug, Copy, Clone)]
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pub struct Registers {
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a: u8,
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b: u8,
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c: u8,
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d: u8,
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e: u8,
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h: u8,
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l: u8,
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f: u8,
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}
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impl Index<Register> for Registers {
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type Output = u8;
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fn index(&self, index: Register) -> &Self::Output {
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match index {
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Register::A => &self.a,
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Register::B => &self.b,
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Register::C => &self.c,
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Register::D => &self.d,
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Register::E => &self.e,
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Register::H => &self.h,
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Register::L => &self.l,
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Register::F => &self.f,
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}
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}
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}
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impl IndexMut<Register> for Registers {
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fn index_mut(&mut self, index: Register) -> &mut Self::Output {
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match index {
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Register::A => &mut self.a,
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Register::B => &mut self.b,
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Register::C => &mut self.c,
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Register::D => &mut self.d,
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Register::E => &mut self.e,
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Register::H => &mut self.h,
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Register::L => &mut self.l,
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Register::F => &mut self.f,
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}
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}
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}
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#[derive(Debug, Copy, Clone)]
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pub enum Register {
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A,
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B,
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C,
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D,
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E,
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H,
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L,
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F,
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}
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#[derive(Debug, Copy, Clone)]
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pub enum RegisterPair {
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AF,
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BC,
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DE,
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HL,
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SP,
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PC,
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}
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impl LR35902 {
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pub fn register_pair(&self, pair: RegisterPair) -> u16 {
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match pair {
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RegisterPair::AF => {
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(self.registers[Register::A] as u16) << 8 | self.registers[Register::F] as u16
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}
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RegisterPair::BC => {
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(self.registers[Register::B] as u16) << 8 | self.registers[Register::C] as u16
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}
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RegisterPair::DE => {
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(self.registers[Register::D] as u16) << 8 | self.registers[Register::E] as u16
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}
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RegisterPair::HL => {
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(self.registers[Register::H] as u16) << 8 | self.registers[Register::L] as u16
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}
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RegisterPair::SP => self.sp,
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RegisterPair::PC => self.pc,
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}
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}
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pub fn set_register_pair(&mut self, pair: RegisterPair, value: u16) {
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let high = (value >> 8) as u8;
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let low = value as u8;
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match pair {
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RegisterPair::AF => {
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self.registers[Register::A] = high;
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self.registers[Register::F] = low;
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}
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RegisterPair::BC => {
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self.registers[Register::B] = high;
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self.registers[Register::C] = low;
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}
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RegisterPair::DE => {
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self.registers[Register::D] = high;
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self.registers[Register::E] = low;
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}
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RegisterPair::HL => {
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self.registers[Register::H] = high;
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self.registers[Register::L] = low;
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}
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RegisterPair::SP => self.sp = value,
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RegisterPair::PC => self.pc = value,
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}
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}
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}
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#[derive(Debug, Copy, Clone)]
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enum Argument {
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Register(Register),
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RegisterPair(RegisterPair),
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IndirectRegisterPair(RegisterPair),
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ImmediateByte(u8),
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ImmediateWord(u16),
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IndirectImmediateByte(u16),
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}
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#[derive(Debug, Copy, Clone)]
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enum Instruction {
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Add(Argument, Argument),
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NOP,
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STOP,
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HALT,
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}
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@ -1,4 +0,0 @@
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pub use cpu::LR35902;
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pub mod bus;
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pub mod cpu;
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