feat: implement all opcodes in rot table
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f9d7fe05df
commit
9be1d1508e
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@ -426,10 +426,9 @@ impl Instruction {
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let a = cpu.register(Register::A);
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let msb = a >> 7;
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let rot_a = (a << 1) | ((flags.c as u8) << 0);
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let (rot_a, carry) = Self::rl_tru_carry(a, flags.c);
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flags.update(false, false, false, msb == 0x01);
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flags.update(false, false, false, carry);
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cpu.set_register(Register::Flag, flags.into());
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cpu.set_register(Register::A, rot_a);
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Cycles(4)
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@ -439,10 +438,9 @@ impl Instruction {
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let a = cpu.register(Register::A);
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let lsb = a & 0x01;
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let rot_a = (a >> 1) | ((flags.c as u8) << 7);
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let (rot_a, carry) = Self::rr_thru_carry(a, flags.c);
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flags.update(false, false, false, lsb == 0x01);
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flags.update(false, false, false, carry);
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cpu.set_register(Register::Flag, flags.into());
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cpu.set_register(Register::A, rot_a);
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Cycles(4)
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@ -990,8 +988,8 @@ impl Instruction {
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Instruction::RLC(reg) => {
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// RLC r[z] | Rotate register r[z] left
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let carry_flag;
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let result;
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let msb;
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let rot_reg;
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let cycles: Cycles;
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match reg {
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@ -1005,34 +1003,34 @@ impl Instruction {
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let register = Register::try_from(reg).unwrap();
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let value = cpu.register(register);
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carry_flag = value >> 7 == 0x01;
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result = value.rotate_left(1);
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msb = value >> 7;
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rot_reg = value.rotate_left(1);
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cpu.set_register(register, result);
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cpu.set_register(register, rot_reg);
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cycles = Cycles(8);
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}
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InstrRegister::IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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let value = cpu.read_byte(addr);
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carry_flag = value >> 7 == 0x01;
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result = value.rotate_left(1);
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msb = value >> 7;
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rot_reg = value.rotate_left(1);
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cpu.write_byte(addr, result);
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cpu.write_byte(addr, rot_reg);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(result == 0, false, false, carry_flag);
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flags.update(rot_reg == 0, false, false, msb == 0x01);
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cpu.set_register(Register::Flag, flags.into());
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cycles
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}
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Instruction::RRC(reg) => {
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// RRC r[z] | Rotate Register r[z] right
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let carry_flag;
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let result;
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let lsb;
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let rot_reg;
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let cycles: Cycles;
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match reg {
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@ -1046,34 +1044,34 @@ impl Instruction {
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let register = Register::try_from(reg).unwrap();
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let value = cpu.register(register);
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carry_flag = value & 0x01 == 0x01;
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result = value.rotate_right(1);
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lsb = value & 0x01;
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rot_reg = value.rotate_right(1);
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cpu.set_register(register, result);
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cpu.set_register(register, rot_reg);
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cycles = Cycles(8);
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}
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InstrRegister::IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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let value = cpu.read_byte(addr);
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carry_flag = value & 0x01 == 0x01;
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result = value.rotate_right(1);
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lsb = value & 0x01;
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rot_reg = value.rotate_right(1);
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cpu.write_byte(addr, result);
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cpu.write_byte(addr, rot_reg);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(result == 0, false, false, carry_flag);
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flags.update(rot_reg == 0, false, false, lsb == 0x01);
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cpu.set_register(Register::Flag, flags.into());
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cycles
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}
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Instruction::RL(reg) => {
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// RL r[z] | Rotate register r[z] left through carry
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let carry_flag;
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let result;
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let carry;
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let rot_reg;
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let cycles: Cycles;
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match reg {
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@ -1086,38 +1084,241 @@ impl Instruction {
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| InstrRegister::A => {
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let register = Register::try_from(reg).unwrap();
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let value = cpu.register(register);
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carry_flag = value >> 7 == 0x01;
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result = value << 1 | flags.c as u8;
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cpu.set_register(register, result);
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let (new_reg, new_carry) = Self::rl_tru_carry(value, flags.c);
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rot_reg = new_reg;
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carry = new_carry;
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cpu.set_register(register, rot_reg);
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cycles = Cycles(8);
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}
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InstrRegister::IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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let value = cpu.read_byte(addr);
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carry_flag = value >> 7 == 0x01;
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result = value << 1 | flags.c as u8;
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cpu.write_byte(addr, result);
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let (new_reg, new_carry) = Self::rl_tru_carry(value, flags.c);
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rot_reg = new_reg;
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carry = new_carry;
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cpu.write_byte(addr, rot_reg);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(result == 0, false, false, carry_flag);
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flags.update(rot_reg == 0, false, false, carry);
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cpu.set_register(Register::Flag, flags.into());
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cycles
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}
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Instruction::RR(reg) => {
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// RR r[z] | Rotate register r[z] right through carry
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let carry_flag;
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let result;
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let carry;
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let rot_reg;
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let cycles: Cycles;
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flags.update(false, false, false, false);
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match reg {
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InstrRegister::B
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| InstrRegister::C
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| InstrRegister::D
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| InstrRegister::E
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| InstrRegister::H
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| InstrRegister::L
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| InstrRegister::A => {
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let register = Register::try_from(reg).unwrap();
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let value = cpu.register(register);
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let (new_reg, new_carry) = Self::rr_thru_carry(value, flags.c);
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rot_reg = new_reg;
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carry = new_carry;
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cpu.set_register(register, rot_reg);
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cycles = Cycles(8);
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}
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InstrRegister::IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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let value = cpu.read_byte(addr);
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let (new_reg, new_carry) = Self::rr_thru_carry(value, flags.c);
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rot_reg = new_reg;
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carry = new_carry;
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cpu.write_byte(addr, rot_reg);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(rot_reg == 0, false, false, carry);
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cpu.set_register(Register::Flag, flags.into());
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cycles
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}
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Instruction::SLA(reg) => {
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// SLA r[z] | Shift left arithmetic register r[z]
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let shift_reg;
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let msb;
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let cycles: Cycles;
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match reg {
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InstrRegister::B
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| InstrRegister::C
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| InstrRegister::D
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| InstrRegister::E
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| InstrRegister::H
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| InstrRegister::L
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| InstrRegister::A => {
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let register = Register::try_from(reg).unwrap();
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let value = cpu.register(register);
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msb = (value >> 7) & 0x01;
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shift_reg = value << 1;
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cpu.set_register(register, shift_reg);
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cycles = Cycles(8);
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}
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InstrRegister::IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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let value = cpu.read_byte(addr);
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msb = (value >> 7) & 0x01;
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shift_reg = value << 1;
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cpu.write_byte(addr, value);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unimplemented!(),
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}
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flags.update(shift_reg == 0, false, false, msb == 0x01);
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cpu.set_register(Register::Flag, flags.into());
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cycles
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}
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Instruction::SRA(reg) => {
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// SRA r[z] | Shift right arithmetic register r[z]
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let shift_reg;
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let lsb;
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let cycles: Cycles;
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match reg {
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InstrRegister::B
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| InstrRegister::C
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| InstrRegister::D
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| InstrRegister::E
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| InstrRegister::H
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| InstrRegister::L
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| InstrRegister::A => {
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let register = Register::try_from(reg).unwrap();
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let value = cpu.register(register);
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lsb = value & 0x01;
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let msb = (value >> 7) & 0x01;
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shift_reg = (value >> 1) | (msb << 7); // msb is duplicated in this op
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cpu.set_register(register, shift_reg);
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cycles = Cycles(8);
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}
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InstrRegister::IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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let value = cpu.read_byte(addr);
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lsb = value & 0x01;
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let msb = (value >> 7) & 0x01;
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shift_reg = (value >> 1) | (msb << 7); // msb is duplicated in this op
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cpu.write_byte(addr, value);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unimplemented!(),
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}
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flags.update(shift_reg == 0, false, false, lsb == 0x01);
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cpu.set_register(Register::Flag, flags.into());
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cycles
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}
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Instruction::SWAP(reg) => {
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// SWAP r[z] | Swap the 4 highest and lowest bits in a byte
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let swap_reg;
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let cycles: Cycles;
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match reg {
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InstrRegister::B
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| InstrRegister::C
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| InstrRegister::D
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| InstrRegister::E
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| InstrRegister::H
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| InstrRegister::L
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| InstrRegister::A => {
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let register = Register::try_from(reg).unwrap();
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let value = cpu.register(register);
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swap_reg = Self::swap_bits(value);
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cpu.set_register(register, swap_reg);
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cycles = Cycles(8);
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}
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InstrRegister::IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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let value = cpu.read_byte(addr);
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swap_reg = Self::swap_bits(value);
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cpu.write_byte(addr, swap_reg);
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cycles = Cycles(16)
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(swap_reg == 0, false, false, false);
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cpu.set_register(Register::Flag, flags.into());
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cycles
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}
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Instruction::SRL(reg) => {
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// SRL r[z] | Shift right logic restier r[z]
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let mut flags: Flags = cpu.register(Register::Flag).into();
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let lsb;
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let shift_reg;
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let cycles: Cycles;
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match reg {
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InstrRegister::B
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| InstrRegister::C
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| InstrRegister::D
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| InstrRegister::E
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| InstrRegister::H
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| InstrRegister::L
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| InstrRegister::A => {
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let register = Register::try_from(reg).unwrap();
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let value = cpu.register(register);
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lsb = value & 0x01;
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shift_reg = value >> 1;
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cpu.set_register(register, shift_reg);
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cycles = Cycles(8);
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}
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InstrRegister::IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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let value = cpu.read_byte(addr);
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lsb = value & 0x01;
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shift_reg = value >> 1;
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cpu.write_byte(addr, shift_reg);
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cycles = Cycles(16);
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}
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InstrRegister::IndirectC => unreachable!(),
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}
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flags.update(shift_reg == 0, false, false, lsb == 0x01);
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cpu.set_register(Register::Flag, flags.into());
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cycles
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@ -1237,6 +1438,27 @@ impl Instruction {
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fn u8_half_carry(left: u8, right: u8) -> bool {
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((left & 0xF) + (right & 0xF)) & 0x10 == 0x10
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}
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fn rl_tru_carry(byte: u8, carry: bool) -> (u8, bool) {
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let carry_flag = (byte >> 7) & 0x01; // get the MSB of the u8 (which will rotate into the carry bit)
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let new_byte = (byte << 1) | carry as u8; // shift the bit left, and then OR the carry bit in.
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(new_byte, carry_flag == 0x01)
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}
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fn rr_thru_carry(byte: u8, carry: bool) -> (u8, bool) {
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let carry_flag = byte & 0x01; // get the LSB of the u8 (which will rotate into the carry bit)
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let new_byte = (byte >> 1) | ((carry as u8) << 7); // shift the bit right, and then OR the carry bit in.
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(new_byte, carry_flag == 0x01)
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}
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fn swap_bits(byte: u8) -> u8 {
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let upper = byte >> 4;
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let lower = byte & 0x0F;
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(lower << 4) | upper
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}
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}
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impl Instruction {
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