fix(cartridge): don't read from RAM that doesn't exist
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continuous-integration/drone/push Build is passing
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@ -217,7 +217,9 @@ impl MBCIo for MBC1 {
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0x4000..=0x7FFF => {
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0x4000..=0x7FFF => {
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Address(0x4000 * self.high_bank() as usize + (addr as usize - 0x4000))
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Address(0x4000 * self.high_bank() as usize + (addr as usize - 0x4000))
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}
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}
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0xA000..=0xBFFF if self.mem_enabled => Value(self.memory[self.ram_addr(addr)]),
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0xA000..=0xBFFF if self.mem_enabled && self.ram_size != RamSize::None => {
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Value(self.memory[self.ram_addr(addr)])
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}
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0xA000..=0xBFFF => Value(0xFF),
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0xA000..=0xBFFF => Value(0xFF),
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_ => unreachable!("A read from {:#06X} should not be handled by MBC1", addr),
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_ => unreachable!("A read from {:#06X} should not be handled by MBC1", addr),
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}
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}
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@ -233,7 +235,7 @@ impl MBCIo for MBC1 {
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}
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}
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0x4000..=0x5FFF => self.ram_bank = byte & 0x03,
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0x4000..=0x5FFF => self.ram_bank = byte & 0x03,
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0x6000..=0x7FFF => self.mode = (byte & 0x01) == 0x01,
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0x6000..=0x7FFF => self.mode = (byte & 0x01) == 0x01,
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0xA000..=0xBFFF if self.mem_enabled => {
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0xA000..=0xBFFF if self.mem_enabled && self.ram_size != RamSize::None => {
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let ram_addr = self.ram_addr(addr);
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let ram_addr = self.ram_addr(addr);
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self.memory[ram_addr] = byte;
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self.memory[ram_addr] = byte;
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}
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}
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@ -503,7 +505,7 @@ impl Default for MBCKind {
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}
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}
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}
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}
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#[derive(Debug, Clone, Copy)]
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#[derive(Debug, Clone, Copy, PartialEq)]
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enum RamSize {
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enum RamSize {
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None = 0x00,
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None = 0x00,
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Unused = 0x01,
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Unused = 0x01,
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