feat: stub work ram

Cargo.toml

@@ -1,7 +1,7 @@
 [package]
 name = "gb"
 version = "0.1.0"
-authors = ["Rekai Musuka <musukarekai@gmail.com>"]
+authors = ["Rekai Musuka <rekai@musuka.dev>"]
 edition = "2018"
 
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html

src/bus.rs

@@ -1,10 +1,13 @@
 use super::cartridge::Cartridge;
 use super::ppu::PPU;
+use super::work_ram::{VariableWorkRAM, WorkRAM};
 #[derive(Debug, Clone)]
 pub struct Bus {
     boot: Option<[u8; 256]>, // Boot ROM is 256b long
     cartridge: Option<Cartridge>,
     ppu: PPU,
+    wram: WorkRAM,
+    vwram: VariableWorkRAM,
 }
 
 impl Default for Bus {
@@ -13,6 +16,8 @@ impl Default for Bus {
             boot: Some(include_bytes!("../bin/DMG_ROM.bin").to_owned()),
             cartridge: None,
             ppu: Default::default(),
+            wram: Default::default(),
+            vwram: Default::default(),
         }
     }
 }
@@ -64,11 +69,11 @@ impl Bus {
             }
             0xC000..=0xCFFF => {
                 // 4KB Work RAM Bank 0
-                unimplemented!("Unable to read {:#06X} in Work RAM Bank 0", addr);
+                self.wram.read_byte((addr - 0xC000) as usize)
             }
             0xD000..=0xDFFF => {
                 // 4KB Work RAM Bank 1 -> N
-                unimplemented!("Unable to read {:#06X} in Work RAM Bank N", addr);
+                self.vwram.read_byte((addr - 0xD000) as usize)
             }
             0xE000..=0xFDFF => {
                 // Mirror of 0xC000 to 0xDDFF
@@ -114,11 +119,11 @@ impl Bus {
             }
             0xC000..=0xCFFF => {
                 // 4KB Work RAM Bank 0
-                unimplemented!("Unable to write to {:#06X} in Work RAM Bank 0", addr);
+                self.wram.write_byte((addr - 0xC000) as usize, byte);
             }
             0xD000..=0xDFFF => {
                 // 4KB Work RAM Bank 1 -> N
-                unimplemented!("Unable to write to {:#06X} in Work RAM Bank N", addr);
+                self.vwram.write_byte((addr - 0xD000) as usize, byte);
             }
             0xE000..=0xFDFF => {
                 // Mirror of 0xC000 to 0xDDFF

src/instruction.rs

@@ -2011,9 +2011,11 @@ impl std::fmt::Debug for LDTarget {
             LDTarget::IndirectRegister(pair) => write!(f, "{:?}", pair),
             LDTarget::ByteAtAddress(addr) => write!(f, "{:#06X}", addr),
             LDTarget::ImmediateWord(word) => write!(f, "{:#06X}", word),
-            LDTarget::ImmediateByte(byte) => write!(f, "{:04X}", byte),
+            LDTarget::ImmediateByte(byte) => write!(f, "{:#04X}", byte),
             LDTarget::RegisterPair(pair) => write!(f, "{:?}", pair),
-            LDTarget::ByteAtAddressWithOffset(byte) => write!(f, "{:#04X}", byte),
+            LDTarget::ByteAtAddressWithOffset(byte) => {
+                write!(f, "{:#04X}", 0xFF00 + byte as u16)
+            }
         }
     }
 }

src/lib.rs

@@ -3,3 +3,4 @@ mod cartridge;
 pub mod cpu;
 mod instruction;
 mod ppu;
+mod work_ram;

src/main.rs

@@ -1,7 +1,7 @@
 use gb::cpu::Cpu as LR35902;
 
 fn main() {
-    let mut game_boy = LR35902::new();
+    let mut game_boy = LR35902::new_without_boot();
 
     game_boy.load_cartridge("bin/cpu_instrs.gb");
 

src/work_ram.rs

@@ -0,0 +1,82 @@
+#[derive(Debug, Clone)]
+pub struct WorkRAM {
+    bank: Box<[u8]>,
+}
+
+impl WorkRAM {
+    pub fn write_byte(&mut self, index: usize, byte: u8) {
+        self.bank[index] = byte;
+    }
+
+    pub fn read_byte(&self, index: usize) -> u8 {
+        self.bank[index]
+    }
+}
+
+impl Default for WorkRAM {
+    fn default() -> Self {
+        Self {
+            bank: vec![0u8; 4096].into_boxed_slice(),
+        }
+    }
+}
+
+#[derive(Debug, Clone, Copy)]
+pub enum BankNumber {
+    One,
+    Two,
+    Three,
+    Four,
+    Five,
+    Six,
+    Seven,
+}
+
+impl From<BankNumber> for usize {
+    fn from(bank_num: BankNumber) -> Self {
+        match bank_num {
+            BankNumber::One => 1,
+            BankNumber::Two => 2,
+            BankNumber::Three => 3,
+            BankNumber::Four => 4,
+            BankNumber::Five => 5,
+            BankNumber::Six => 6,
+            BankNumber::Seven => 7,
+        }
+    }
+}
+
+#[derive(Debug, Clone)]
+pub struct VariableWorkRAM {
+    current: BankNumber,
+    bank_n: Box<[[u8; 4096]]>, // 4K for Variable amount of Banks (Banks 1 -> 7) in Game Boy Colour
+}
+
+impl Default for VariableWorkRAM {
+    fn default() -> Self {
+        Self {
+            current: BankNumber::One,
+            bank_n: vec![[0u8; 4096]; 7].into_boxed_slice(),
+        }
+    }
+}
+
+impl VariableWorkRAM {
+    pub fn set_current_bank(&mut self, bank: BankNumber) {
+        self.current = bank;
+    }
+
+    pub fn get_current_bank(&self) -> BankNumber {
+        self.current
+    }
+
+    pub fn write_byte(&mut self, index: usize, byte: u8) {
+        let num: usize = self.current.into();
+        self.bank_n[num][index] = byte;
+    }
+
+    pub fn read_byte(&self, index: usize) -> u8 {
+        let num: usize = self.current.into();
+        self.bank_n[num][index]
+    }
+}