chore(cpu): rename discriminants of ImeState enum
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parent
53dfaf0de2
commit
8c9567b610
19
src/cpu.rs
19
src/cpu.rs
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@ -118,7 +118,7 @@ impl Cpu {
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let opcode = self.fetch();
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let opcode = self.fetch();
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let instr = self.decode(opcode);
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let instr = self.decode(opcode);
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let elapsed = self.execute(instr);
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let elapsed = self.execute(instr);
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self.check_ime();
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self.handle_ei();
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elapsed
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elapsed
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}
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}
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};
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};
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@ -159,18 +159,11 @@ impl Cpu {
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&mut self.bus.joypad
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&mut self.bus.joypad
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}
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}
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fn check_ime(&mut self) {
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fn handle_ei(&mut self) {
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match self.ime {
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match self.ime {
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ImeState::Pending => {
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ImeState::EiExecuted => self.ime = ImeState::Pending,
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// This is within the context of the EI instruction, we need to not update EI until the end of the
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ImeState::Pending => self.ime = ImeState::Enabled,
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// next executed Instruction
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ImeState::Disabled | ImeState::Enabled => {}
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self.ime = ImeState::PendingEnd;
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}
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ImeState::PendingEnd => {
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// The Instruction after EI has now been executed, so we want to enable the IME flag here
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self.ime = ImeState::Enabled;
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}
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ImeState::Disabled | ImeState::Enabled => {} // Do Nothing
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}
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}
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}
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}
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@ -514,8 +507,8 @@ pub(crate) enum HaltState {
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#[derive(Debug, Clone, Copy)]
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#[derive(Debug, Clone, Copy)]
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pub(crate) enum ImeState {
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pub(crate) enum ImeState {
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Disabled,
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Disabled,
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EiExecuted,
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Pending,
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Pending,
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PendingEnd,
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Enabled,
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Enabled,
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}
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}
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@ -971,7 +971,7 @@ impl Instruction {
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}
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}
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Instruction::EI => {
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Instruction::EI => {
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// EI | Enable IME after the next instruction
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// EI | Enable IME after the next instruction
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cpu.set_ime(ImeState::Pending);
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cpu.set_ime(ImeState::EiExecuted);
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Cycle::new(4)
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Cycle::new(4)
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}
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}
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Instruction::CALL(cond) => {
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Instruction::CALL(cond) => {
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