Restart GB Emulator
This commit is contained in:
Rekai Musuka
parent
9032716346
commit
8b475cb4cf
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@ -0,0 +1,14 @@
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#[derive(Debug, Copy, Clone)]
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pub struct MemoryBus {
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}
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impl MemoryBus {
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pub fn read_byte(&self, _address: u16) {
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unimplemented!()
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}
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pub fn write_byte(&self, _address: u16) {
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unimplemented!()
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}
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}
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398
src/cpu.rs
398
src/cpu.rs
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@ -1,365 +1,91 @@
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// use super::instructions::Instruction;
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use super::bus::MemoryBus;
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use std::ops::{Index, IndexMut};
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use std::convert::From;
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// Gameboy CPU
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#[derive(Debug, Copy, Clone)]
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pub struct LR35902 {
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_sp: u16,
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_pc: u16,
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_reg: Registers,
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bus: MemoryBus,
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registers: Registers,
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sp: u16, // Stack Pointer
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pc: u16, // Program Counter
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flag: Flag, // Flag Register
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ime: bool, // Interrupt Master Enable Flag
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}
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impl LR35902 {
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pub fn cycle(&mut self) {
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let opcode = Self::fetch();
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self.decode(opcode);
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Self::execute();
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}
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#[derive(Debug, Copy, Clone)]
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pub struct Flag {
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z: bool, // Zero Flag
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n: bool, // Subtract Flag
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h: bool, // Half-Carry Flag
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c: bool, // Carry Flag
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}
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fn fetch() -> u8 {
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unimplemented!()
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}
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fn decode(&mut self, opcode: u8) {
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// Source: https://gb-archive.github.io/salvage/decoding_gbz80_opcodes/Decoding%20Gamboy%20Z80%20Opcodes.html
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// x = the opcode's 1st octal digit (i.e. bits 7-6)
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// y = the opcode's 2nd octal digit (i.e. bits 5-3)
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// z = the opcode's 3rd octal digit (i.e. bits 2-0)
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// p = y right-shifted one position (i.e. bits 5-4)
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// q = y modulo 2 (i.e. bit 3)
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let x = opcode >> 6;
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let y = (opcode & 0b00111000) >> 3; // 0b00111000 = 0x38
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let z = opcode & 0b00000111; // 0b00000111 = 0x07
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let p = y >> 1;
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let q = y & 0b00000001; // 0b001 = 0x1;
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let _d: i8 = 0; // Displacement Byte
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let _n: u8 = 0; // 8-bit Immediate Operand
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let _nn: u16 = 0; // 16-bit Immediate Operand
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match (x, z, q, y, p) {
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(0, 0, _, 0, _) => {}
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_ => panic!("Unexpected Opcode!"),
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impl From<u8> for Flag {
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fn from(num: u8) -> Self {
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Flag {
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z: (num >> 7) == 1,
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n: ((num >> 6) & 0x01) == 1,
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h: ((num >> 5) & 0x01) == 1,
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c: ((num >> 4) & 0x01) == 1,
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}
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}
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fn execute() {
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unimplemented!()
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}
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impl From<Flag> for u8 {
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fn from(flag: Flag) -> Self {
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(flag.z as u8) << 7 | (flag.n as u8) << 6 | (flag.h as u8) << 5 | (flag.c as u8) << 4
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}
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}
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#[derive(Debug, Copy, Clone, Default)]
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#[derive(Debug, Copy, Clone)]
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pub struct Registers {
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a: u8, // Accumulator Register
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a: u8,
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b: u8,
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c: u8,
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d: u8,
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e: u8,
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h: u8,
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l: u8,
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f: Flag,
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}
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impl Registers {
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pub fn set_af(&mut self, value: u16) {
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let (high, low) = Self::split_u16(value);
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impl Index<Register> for Registers {
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type Output = u8;
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self.a = high;
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self.f = low.into();
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}
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pub fn get_af(&self) -> u16 {
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Self::merge_u8s(self.a, self.f.into())
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}
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pub fn set_bc(&mut self, value: u16) {
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let (high, low) = Self::split_u16(value);
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self.b = high;
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self.c = low;
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}
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pub fn get_bc(&self) -> u16 {
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Self::merge_u8s(self.b, self.c)
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}
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pub fn set_de(&mut self, value: u16) {
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let (high, low) = Self::split_u16(value);
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self.d = high;
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self.e = low;
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}
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pub fn get_de(&self) -> u16 {
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Self::merge_u8s(self.d, self.e)
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}
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pub fn set_hl(&mut self, value: u16) {
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let (high, low) = Self::split_u16(value);
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self.h = high;
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self.l = low;
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}
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pub fn get_hl(&self) -> u16 {
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Self::merge_u8s(self.h, self.l)
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}
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pub fn set_a(&mut self, a: u8) {
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self.a = a;
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}
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pub fn get_a(&self) -> u8 {
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self.a
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}
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pub fn set_b(&mut self, b: u8) {
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self.b = b;
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}
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pub fn get_b(&self) -> u8 {
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self.b
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}
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pub fn set_c(&mut self, c: u8) {
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self.c = c;
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}
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pub fn get_c(&self) -> u8 {
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self.c
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}
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pub fn set_d(&mut self, d: u8) {
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self.d = d;
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}
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pub fn get_d(&self) -> u8 {
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self.d
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}
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pub fn set_e(&mut self, e: u8) {
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self.e = e;
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}
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pub fn get_e(&self) -> u8 {
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self.e
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}
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pub fn set_h(&mut self, h: u8) {
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self.h = h;
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}
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pub fn get_h(&self) -> u8 {
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self.h
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}
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pub fn set_l(&mut self, l: u8) {
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self.l = l;
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}
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pub fn get_l(&self) -> u8 {
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self.l
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}
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pub fn set_f<F: Into<Flag>>(&mut self, flag: F) {
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self.f = flag.into();
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}
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pub fn get_f(&self) -> Flag {
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self.f
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}
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pub fn get_u8_f(&self) -> u8 {
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self.f.into()
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}
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fn split_u16(value: u16) -> (u8, u8) {
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((value >> 8) as u8, value as u8)
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}
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fn merge_u8s(left: u8, right: u8) -> u16 {
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(left as u16) << 8 | right as u16
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}
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}
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#[derive(Debug, Copy, Clone, Default)]
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pub struct Flag(u8);
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impl Flag {
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pub fn get_zf(&self) -> bool {
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(self.0 >> 7) == 1
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}
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pub fn set_zf(&mut self, enabled: bool) {
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if enabled {
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self.0 |= 0b10000000; // Set
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} else {
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self.0 &= 0b01111111; // Clear
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}
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}
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pub fn get_n(&self) -> bool {
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((self.0 >> 6) & 0x01) == 1
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}
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pub fn set_n(&mut self, enabled: bool) {
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if enabled {
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self.0 |= 0b01000000; // Set
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} else {
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self.0 &= 0b10111111; // Clear
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}
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}
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pub fn get_h(&self) -> bool {
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((self.0 >> 5) & 0x01) == 1
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}
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pub fn set_h(&mut self, enabled: bool) {
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if enabled {
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self.0 |= 0b00100000; // Set
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} else {
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self.0 &= 0b11011111; // Clear
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}
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}
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pub fn get_cy(&self) -> bool {
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((self.0 >> 4) & 0x01) == 1
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}
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pub fn set_cy(&mut self, enabled: bool) {
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if enabled {
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self.0 |= 0b00010000; // Set
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} else {
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self.0 &= 0b11101111; // Clear
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fn index(&self, index: Register) -> &Self::Output {
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match index {
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Register::A => &self.a,
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Register::B => &self.b,
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Register::C => &self.c,
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Register::D => &self.d,
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Register::E => &self.e,
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Register::H => &self.h,
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Register::L => &self.l,
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}
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}
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}
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impl From<u8> for Flag {
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fn from(value: u8) -> Self {
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Self(value & 0xF0) // Throw out bits 0 -> 3
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impl IndexMut<Register> for Registers {
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fn index_mut(&mut self, index: Register) -> &mut Self::Output {
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match index {
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Register::A => &mut self.a,
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Register::B => &mut self.b,
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Register::C => &mut self.c,
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Register::D => &mut self.d,
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Register::E => &mut self.e,
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Register::H => &mut self.h,
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Register::L => &mut self.l,
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}
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}
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}
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impl From<Flag> for u8 {
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fn from(flag: Flag) -> Self {
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flag.0
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}
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}
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#[cfg(test)]
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mod test {
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use super::*;
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#[test]
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fn flag_zf_works() {
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let mut flag: Flag = Default::default();
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flag.set_zf(true);
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assert_eq!(u8::from(flag), 0b10000000);
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assert!(flag.get_zf());
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flag.set_zf(false);
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assert_eq!(u8::from(flag), 0b00000000);
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assert!(!flag.get_zf());
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}
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#[test]
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fn flag_n_works() {
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let mut flag: Flag = Default::default();
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flag.set_n(true);
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assert_eq!(u8::from(flag), 0b01000000);
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assert!(flag.get_n());
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flag.set_n(false);
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assert_eq!(u8::from(flag), 0b00000000);
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assert!(!flag.get_n());
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}
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#[test]
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fn flag_h_works() {
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let mut flag: Flag = Default::default();
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flag.set_h(true);
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assert_eq!(u8::from(flag), 0b00100000);
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assert!(flag.get_h());
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flag.set_h(false);
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assert_eq!(u8::from(flag), 0b00000000);
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assert!(!flag.get_h());
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}
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#[test]
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fn flags_work_together() {
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let mut flag: Flag = Default::default();
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assert_eq!(u8::from(flag), 0b00000000);
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flag.set_zf(true);
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flag.set_cy(true);
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flag.set_h(true);
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flag.set_n(true);
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assert_eq!(u8::from(flag), 0b11110000);
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assert!(flag.get_zf());
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assert!(flag.get_n());
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assert!(flag.get_h());
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assert!(flag.get_cy());
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flag.set_cy(false);
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assert_eq!(u8::from(flag), 0b11100000);
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assert!(!flag.get_cy());
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flag.set_n(false);
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assert_eq!(u8::from(flag), 0b10100000);
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assert!(!flag.get_n());
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}
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#[test]
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fn flag_to_u8_and_back_works() {
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let flag: Flag = 0b10011111.into();
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assert_eq!(u8::from(flag), 0b10010000);
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assert_eq!(flag.0, 0b10010000);
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assert!(flag.get_zf());
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assert!(!flag.get_n());
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assert!(!flag.get_h());
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assert!(flag.get_cy());
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let mut base: Flag = Default::default();
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base.set_h(true);
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base.set_zf(true);
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assert_eq!(base.0, 0b10100000);
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assert_eq!(u8::from(base), 0b10100000);
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}
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#[test]
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fn flag_cy_works() {
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let mut flag: Flag = Default::default();
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flag.set_cy(true);
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assert_eq!(u8::from(flag), 0b00010000);
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assert!(flag.get_cy());
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flag.set_cy(false);
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assert_eq!(u8::from(flag), 0b00000000);
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assert!(!flag.get_cy());
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}
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#[test]
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fn split_u16_works() {
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let num = 0xABCD;
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let (high, low) = Registers::split_u16(num);
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assert_eq!(high, 0xAB);
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assert_eq!(low, 0xCD);
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}
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#[test]
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fn merge_u8s_works() {
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let left = 0xAB;
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let right = 0xCD;
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let res = Registers::merge_u8s(left, right);
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assert_eq!(res, 0xABCD);
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}
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#[derive(Debug, Copy, Clone)]
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pub enum Register {
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A,
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B,
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C,
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D,
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E,
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H,
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L,
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}
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@ -1,389 +0,0 @@
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use super::cpu::Flag;
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/// Sharp SM83 Instructions
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/// ### Definitions
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/// * "Any valid 8-bit register" refers to the registers `B`, `C`, `D`, `E`, `H` and `L`.
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/// * If `A` is also a valid register, it will be **explicitly** stated as such.
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/// * "Any valid 16-bit register" refers to the registers BC, DE and HL.
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/// * If `AF` is a valid register, it will be **explicitly** stated as such.
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/// * If `SP` is a valid register, it will be **explicitly** stated as such.
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/// * the value of any 16-bit register in brackets is the value of the data located at
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/// the address of the 16-bit register.
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/// * e.g. the value of `(HL)` would be what is at `memory[cpu.reg.get_hl()]`
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/// * Since the value is from memory, the value is an 8-bit integer.
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pub struct Instruction {}
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impl Instruction {
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// *** 8-bit Loads ***
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/// `LD nn, n` Store value nn in n.
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/// ### Arguments
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/// * `nn` Any valid 8-bit or 16-bit register (including `SP`).
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/// * `n` An 8-bit immediate value.
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pub fn ld_nn_n(nn: u16, n: &mut u8) {
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unimplemented!()
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}
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/// `LD r, r` Store value r2 into r1.
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/// ### Arguments
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/// * `r1` Any valid 8-bit register (including `A`), and `(HL)`.
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/// * `r2` Any valid 8-bit register (including `A`), and `(HL)`.
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pub fn ld_r1_r2(r1: &mut u8, r2: u8) {
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unimplemented!()
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}
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/// `LD A, n` Store value n into register A.
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/// ### Arguments
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/// * `a` The A register
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/// * `n` Any valid 8-bit register (including `A`),`(BC)`, `(DE)`, `(HL)`, `(nn)`, and `#`.
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/// * `nn` A two byte immediate value (Least significant byte first).
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pub fn ld_a_n(a: &mut u8, n: u8) {
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unimplemented!()
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}
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/// `LD n, A` Store register A into n.
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/// ### Arguments
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/// * `n` Any valid 8-bit register (including `A`), `(BC)`, `(DE)`, `(HL)`, and `(nn)`.
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/// * `nn` A two byte immediate value (Least significant byte first).
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/// * `a` The A register.
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pub fn ld_n_a(n: &mut u8, a: u8) {
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unimplemented!()
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}
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/// `LD A, (C)` Store value at $FF00 + register C in register A.
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/// ### Arguments
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/// * `a` The A register.
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/// * `c` The C register.
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pub fn ld_a_c(a: &mut u8, c: u8) {
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unimplemented!()
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}
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/// `LD (C) ,A` Store the value of register A into $FF00 + register C.
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/// ### Arguments
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/// * `c` The C register.
|
||||
/// * `a` The A register.
|
||||
pub fn ld_c_a(c: u8, a: u8) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
// `LD A, (HLD)` is identical to `LDD A, (HL)`.
|
||||
// `LD A, (HL-)` is identical to `LDD A, (HL)`.
|
||||
|
||||
/// `LDD A, (HL)` Put value at $HL into A, then decrement HL.
|
||||
///
|
||||
/// Identical to `LD A, (HLD)`, and `LD A, (HL-)`.
|
||||
/// ### Arguments
|
||||
/// * `a` The A register.
|
||||
/// * `hl` The HL register
|
||||
pub fn ldd_a_hl(a: &mut u8, hl: u16) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
// `LD (HLD), A` is identical to `LDD (HL), A`.
|
||||
// `LD (HL-), A` is identical to `LDD (HL), A`.
|
||||
|
||||
/// `LDD (HL), A` Store register A in $HL, then decrement HL.
|
||||
///
|
||||
/// Identical to `LD (HLD), A`, and `LD (HL-), A`
|
||||
/// ### Arguments
|
||||
/// * `hl` The HL register.
|
||||
/// * `a` The A register.
|
||||
pub fn ldd_hl_a(hl: u16, a: u8) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
// `LD A, (HLI)` is identical to `LDI A, (HL)`.
|
||||
// `LD A, (HL+)` is identical to `LDI A, (HL)`.
|
||||
|
||||
/// `LDI A, (HL)` Store value at $HL in register A, then increment HL.
|
||||
///
|
||||
/// Identical to `LD A, (HLI)`, and `LD A, (HL+)`.
|
||||
/// ### Arguments
|
||||
/// * `a` The A register.
|
||||
/// * `hl` The HL register.
|
||||
pub fn ldi_a_hl(a: &mut u8, hl: u16) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
// `LD (HLI), A` is identical to `LDI (HL), A`.
|
||||
// `LD (HL+), A` is identical to `LDI (HL), A`.
|
||||
|
||||
/// `LDI (HL), A` Store register A in $HL, then increment HL.
|
||||
///
|
||||
/// Identical to `LD (HLI), A`, and `LD (HL+), A`.
|
||||
/// ### Arguments
|
||||
/// * `hl` The HL register.
|
||||
/// * `a` The A register.
|
||||
pub fn ldi_hl_a(hl: u16, a: u8) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `LDH (n), A` Store register A into address $FF00 + n.
|
||||
/// ### Arguments
|
||||
/// * `n` An 8-bit immediate value.
|
||||
/// * `a` The A register.
|
||||
pub fn ldh_n_a(n: u8, a: u8) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `LDH A, (n)` Store address $FF00 + n in the A register.
|
||||
/// ### Arguments
|
||||
/// * `a` The A register.
|
||||
/// * `n` An 8-bit immediate value
|
||||
pub fn ldh_a_n(a: &mut u8, n: u8) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
// *** 16-bit Loads ***
|
||||
|
||||
/// `LD n, nn` Store value nn in n.(really?)
|
||||
/// ### Arguments
|
||||
/// * `n` Any 16-bit register (including `SP`).
|
||||
/// * `nn` A 16-bit immediate value.
|
||||
pub fn ld_n_nn(n: &mut u16, nn: u16) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `LD SP, HL` Put HL into the stack pointer.
|
||||
/// ### Arguments
|
||||
/// * `sp` The stack pointer register.
|
||||
/// * `hl` The HL register.
|
||||
pub fn ld_sp_hl(sp: &mut u16, hl: u16) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
// `LD HL, SP + n` is identical to `LDHL SP, n`.
|
||||
|
||||
/// `LDHL SP, n` "Put SP + n effective address into HL".
|
||||
/// ### Arguments
|
||||
/// * `hl` The HL register.
|
||||
/// * `sp` The stack pointer register.
|
||||
/// * `n` 8-bit **signed** integer.
|
||||
/// * `f` CPU flags.
|
||||
///
|
||||
/// ### Flags
|
||||
/// * `ZF` Reset.
|
||||
/// * `N` Reset.
|
||||
/// * `H` Set / Reset depending on operation.
|
||||
/// * `CY` Set / Reset depending on operation.
|
||||
pub fn ldhl_sp_n(hl: &mut u16, sp: u16, n: i8, f: &mut Flag) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `LD (nn), SP` Store stack pointer at $nn.
|
||||
/// ### Arguments
|
||||
/// * `nn` A 16-bit immediate address.
|
||||
/// * `sp` The stack pointer register.
|
||||
pub fn ld_nn_sp(nn: u16, sp: u16) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `PUSH nn` Push 16-bit register onto the stack, then
|
||||
/// decrement the stack pointer twice.
|
||||
/// ### Arguments
|
||||
/// * `nn` Any valid 16-bit address (including `AF`).
|
||||
/// * `sp` The stack pointer register.
|
||||
/// * `stack` The stack.
|
||||
pub fn push_nn(nn: u16, sp: &mut u16, stack: &[u16]) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `POP nn` Pop two bytes of the stack into register pair nn,
|
||||
/// then increment the stack pointer twice.
|
||||
/// ### Arguments
|
||||
/// `nn` Any valid 16-bit address (including `AF`).
|
||||
/// `sp` The stack pointer register.
|
||||
/// `stack` The stack.
|
||||
pub fn pop_nn(nn: &mut u16, sp: &mut u16, stack: &[u16]) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
// *** 8-bit ALU ***
|
||||
|
||||
/// `ADD A, n` Add n to register A.
|
||||
/// ### Arguments
|
||||
/// `A` The A register
|
||||
/// `nn` Any valid 8-bit register (including `A`), `(HL)`, and `#`.
|
||||
///
|
||||
/// ### Flags
|
||||
/// `ZF` Set if result is zero..
|
||||
/// `N` Reset.
|
||||
/// `H` Set if carry from bit 3.
|
||||
/// `CY` Set if carry from bit 7.
|
||||
pub fn add_a_n(a: &mut u8, n: u8) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `ADC A, n` Add n + carry flag to register A.
|
||||
/// ### Arguments
|
||||
/// `A` The A register.
|
||||
/// `n` Any valid 8-bit register (including `A`), `(HL)`, and `#`.
|
||||
///
|
||||
/// ### Flags
|
||||
/// `ZF` Set if result is zero.
|
||||
/// `N` Reset.
|
||||
/// `H` Set if carry from bit 3.
|
||||
/// `CY` Set if carry from bit 7.
|
||||
pub fn adc_a_n(a: &mut u8, n: u8, f: &mut Flag) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `SUB n` or `SUB A, n` Subtract n from register A.
|
||||
/// ### Arguments
|
||||
/// `A` The A register.
|
||||
/// `n` Any valid 8-bit register (including `A`), `(HL)`, and `#`.
|
||||
///
|
||||
/// ### Flags
|
||||
/// `ZF` Set if result is 0.
|
||||
/// `N` Set.
|
||||
/// `H` Set if no borrow from bit 4.
|
||||
/// `CY` Set if no borrow.
|
||||
pub fn sub_a_n(a: &mut u8, n: u8) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `SBC A, n` Subtract n + carry flag from register A.
|
||||
/// ### Arguments
|
||||
/// `A` The A register.
|
||||
/// `n` Any valid 8-bit register (including `A`), `(HL)`, and `#`.
|
||||
///
|
||||
/// ### Flags
|
||||
/// `ZF` Set if result is 0.
|
||||
/// `N` Set.
|
||||
/// `H` Set if no borrow from bit 4.
|
||||
/// `CY` Set if no borrow.
|
||||
pub fn sbc_a_n(a: &mut u8, n: u8, f: &mut Flag) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `AND n` or `AND A, n` AND n with register A,
|
||||
/// then store the result in register A.
|
||||
/// ### Arguments
|
||||
/// `A` The A register.
|
||||
/// `n` Any valid 8-bit register (including `A`), `(HL)`, and `#`.
|
||||
///
|
||||
/// ### Flags
|
||||
/// `ZF` Set if result is zero.
|
||||
/// `N` Reset
|
||||
/// `H` Set
|
||||
/// `CY` Reset
|
||||
pub fn and_a_n(a: &mut u8, n: u8, f: &mut Flag) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `OR n` or `OR A, n` OR n with register A, then store the result in register A
|
||||
/// ### Arguments
|
||||
/// `A` The A register.
|
||||
/// `n` Any valid 8-bit register (including `A`), `(HL)`, and `#`.
|
||||
///
|
||||
/// ### Flags
|
||||
/// `ZF` Set if result is zero.
|
||||
/// `N` Reset.
|
||||
/// `H` Reset.
|
||||
/// `CY` Reset.
|
||||
pub fn or_a_n(a: &mut u8, n: u8, f: &mut Flag) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `XOR n` or `XOR A, n` XOR n with register A, then store the result in register A.
|
||||
/// ### Arguments
|
||||
/// `A` The A register.
|
||||
/// `n` Any valid -bit register (including `A`), `(HL)`, and `#`.
|
||||
///
|
||||
/// ### Flags
|
||||
/// `ZF` Set if result is zero.
|
||||
/// `N` Reset.
|
||||
/// `H` Reset.
|
||||
/// `CY` Reset.
|
||||
pub fn xor_a_n(a: &mut u8, n: u8) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `CP n` or `CP A, n` Compare register A with n.
|
||||
///
|
||||
/// Note: This is equivalent with `SUB A, n` except that the result of the
|
||||
/// subtraction is discarded. Only the flags are mutated.
|
||||
/// ### Arguments
|
||||
/// `A` The A register.
|
||||
/// `n` Any valid 8-bit register (including `A`), `(HL)`, and `#`.
|
||||
///
|
||||
/// ### Flags
|
||||
/// `ZF` Set if result is zero ( A == n ).
|
||||
/// `N` Set.
|
||||
/// `H` Set if no borrow from bit 4.
|
||||
/// `CY` Set for no borrow. ( A < n ).
|
||||
pub fn cp_a_n(a: u8, n: u8) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `INC n` Increment register n.
|
||||
/// ### Arguments
|
||||
/// `n` Any valid 8-bit register (including `A`), and `(HL)`.
|
||||
///
|
||||
/// ### Flags
|
||||
/// `ZF` Set if result is zero.
|
||||
/// `N` Reset.
|
||||
/// `H` Set if carry from bit 3.
|
||||
/// `CY` Not affected.
|
||||
pub fn inc_n(n: &mut u8) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `DEC n` decrement register n.
|
||||
/// ### Arguments
|
||||
/// `n` Any 8-bit register (including `A`), and `(HL)`.
|
||||
///
|
||||
/// ### Flags
|
||||
/// `ZF` Set if result is zero.
|
||||
/// `N` Set.
|
||||
/// `H` Set if no borrow from bit 4.
|
||||
/// `CY` Not affected.
|
||||
pub fn dec_n(n: &mut u8) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
// *** 16-bit Arithmetic ***
|
||||
|
||||
/// `ADD HL, n` Add n to HL.
|
||||
/// ### Arguments
|
||||
/// `hl` The HL register.
|
||||
/// `n` Any valid 16-bit address (including `SP`).
|
||||
///
|
||||
/// ### Flags
|
||||
/// `ZF` Not affected
|
||||
/// `N` Reset
|
||||
/// `H` Set if carry from bit 11.
|
||||
/// `CY` Set if carry from bit 15.
|
||||
pub fn add_hl_n(hl: &mut u16, n: u16) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `ADD SP, n` Add n to the stack pointer.
|
||||
/// ### Arguments
|
||||
/// `sp` The stack pointer register.
|
||||
/// `n` AN 8-bit signed immediate value (#).
|
||||
///
|
||||
/// ### Flags
|
||||
/// `ZF` Reset
|
||||
/// `N` Reset
|
||||
/// `H` Set or reset according to operation.
|
||||
/// `CY` Set or reset according to operation.
|
||||
pub fn add_sp_n(sp: &mut u16, n: i8) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `INC nn` Increment register nn
|
||||
/// ### Arguments
|
||||
/// `nn` Any valid 16-bit register (including `SP`)
|
||||
pub fn inc_nn(nn: &mut u16) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
/// `DEC nn` Increment register nn
|
||||
/// ### Arguments
|
||||
/// `nn` Any valid 16-bit register (including `SP`)
|
||||
pub fn dec_nn(nn: &mut u16) {
|
||||
unimplemented!()
|
||||
}
|
||||
|
||||
// *** Miscellaneous ***
|
||||
}
|
||||
|
|
@ -1,2 +1,4 @@
|
|||
pub use cpu::LR35902;
|
||||
|
||||
pub mod bus;
|
||||
pub mod cpu;
|
||||
pub mod instructions;
|
||||
|
|
|
|||
Loading…
Reference in New Issue