feat: clock bus on instruction read-write

Commit also includes general work towards passing mem-timings.

Note: while cpu_instrs.gb passes, instr_timing.gb and mem_timing.gb both
are stuck in infinite loops (Currently, it seems like a timing issue).
This is a major regression that hopefully shouldn't last for too long.

src/ppu.rs

@@ -70,7 +70,7 @@ impl BusIo for Ppu {
 }
 
 impl Ppu {
-    pub(crate) fn clock(&mut self) {
+    pub(crate) fn tick(&mut self) {
         self.cycle += 1;
 
         if !self.ctrl.lcd_enabled() {