feat: clock bus on instruction read-write

Commit also includes general work towards passing mem-timings.

Note: while cpu_instrs.gb passes, instr_timing.gb and mem_timing.gb both
are stuck in infinite loops (Currently, it seems like a timing issue).
This is a major regression that hopefully shouldn't last for too long.

src/ppu/dma.rs

@@ -9,7 +9,7 @@ pub(crate) struct DirectMemoryAccess {
 }
 
 impl DirectMemoryAccess {
-    pub(crate) fn clock(&mut self) -> Option<(u16, u16)> {
+    pub(crate) fn tick(&mut self) -> Option<(u16, u16)> {
         match self.state {
             DmaState::Pending => {
                 self.cycle += 1;