feat: clock bus on instruction read-write

Commit also includes general work towards passing mem-timings.

Note: while cpu_instrs.gb passes, instr_timing.gb and mem_timing.gb both
are stuck in infinite loops (Currently, it seems like a timing issue).
This is a major regression that hopefully shouldn't last for too long.

src/apu.rs

@@ -94,7 +94,7 @@ impl BusIo for Apu {
 }
 
 impl Apu {
-    pub(crate) fn clock(&mut self, div: u16) {
+    pub(crate) fn tick(&mut self, div: u16) {
         use FrameSequencerState::*;
         self.sample_counter += SAMPLE_INCREMENT;