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feat: clock bus on instruction read-write
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Commit also includes general work towards passing mem-timings.

Note: while cpu_instrs.gb passes, instr_timing.gb and mem_timing.gb both
are stuck in infinite loops (Currently, it seems like a timing issue).
This is a major regression that hopefully shouldn't last for too long.
This commit is contained in:
Rekai Nyangadzayi Musuka
2021-08-14 00:10:51 -05:00
parent 0637b771e3
commit 8625bec059
9 changed files with 332 additions and 219 deletions
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src/apu/gen.rs
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@@ -3,7 +3,7 @@ use rtrb::{Consumer, Producer, PushError, RingBuffer};
pub(crate) const SAMPLE_RATE: u32 = 48000; // Hz
const CHANNEL_COUNT: usize = 2;
const BUFFER_CAPACITY: usize = 4096 * CHANNEL_COUNT; // # of samples * the # of channels
const BUFFER_CAPACITY: usize = 512 * CHANNEL_COUNT; // # of samples * the # of channels
pub struct AudioSPSC<T> {
inner: RingBuffer<T>,