chore(cpu): document fetch, decode, execute
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14
src/cpu.rs
14
src/cpu.rs
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@ -75,6 +75,8 @@ impl Cpu {
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}
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}
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impl Cpu {
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impl Cpu {
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/// Fetch an [Instruction] from the memory bus
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/// (4 cycles)
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fn fetch(&mut self) -> u8 {
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fn fetch(&mut self) -> u8 {
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let byte = self.read_byte(self.reg.pc);
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let byte = self.read_byte(self.reg.pc);
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self.bus.clock();
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self.bus.clock();
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@ -82,6 +84,10 @@ impl Cpu {
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byte
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byte
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}
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}
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/// Decode a byte into an [SM83](Cpu) [Instruction]
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///
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/// If opcode == 0xCB, then decoding costs 4 cycles.
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/// Otherwise, decoding is free
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pub(crate) fn decode(&mut self, opcode: u8) -> Instruction {
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pub(crate) fn decode(&mut self, opcode: u8) -> Instruction {
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if opcode == 0xCB {
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if opcode == 0xCB {
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Instruction::decode(self.fetch(), true)
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Instruction::decode(self.fetch(), true)
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@ -90,10 +96,18 @@ impl Cpu {
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}
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}
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}
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}
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/// Execute an [Instruction].
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///
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/// The amount of cycles necessary to execute an instruction range from
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/// 0 to 20 T-cycles
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fn execute(&mut self, instruction: Instruction) -> Cycle {
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fn execute(&mut self, instruction: Instruction) -> Cycle {
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Instruction::execute(self, instruction)
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Instruction::execute(self, instruction)
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}
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}
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/// Perform the [`Cpu::fetch()`] [`Cpu::decode(opcode)`] [`Cpu::execute(instr)`]
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/// routine.
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///
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/// Handle HALT state and interrupts.
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pub fn step(&mut self) -> Cycle {
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pub fn step(&mut self) -> Cycle {
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// // Log instructions
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// // Log instructions
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// if self.reg.pc > 0xFF {
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// if self.reg.pc > 0xFF {
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