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chore: rename some symbols

This commit is contained in:
Rekai Nyangadzayi Musuka 2021-04-04 01:31:31 -05:00
parent 4dd7a0d9ce
commit 777abd1c10
3 changed files with 14 additions and 13 deletions
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2
src/bus.rs
View File

@ -235,7 +235,7 @@ impl Bus {
self.ppu.pos.ly_compare = byte; self.ppu.pos.ly_compare = byte;
// Update Coincidence Flag // Update Coincidence Flag
if self.ppu.stat.coincidence_intr() { if self.ppu.stat.coincidence_int() {
let are_equal = self.ppu.pos.line_y == byte; let are_equal = self.ppu.pos.line_y == byte;
self.ppu.stat.set_coincidence(are_equal); self.ppu.stat.set_coincidence(are_equal);
} }

18
src/ppu.rs
View File

@ -56,7 +56,7 @@ impl Ppu {
if self.cycles >= 172.into() { if self.cycles >= 172.into() {
self.cycles %= 172; self.cycles %= 172;
if self.stat.hblank_intr() { if self.stat.hblank_int() {
self.interrupt.set_lcd_stat(true); self.interrupt.set_lcd_stat(true);
} }
@ -73,13 +73,13 @@ impl Ppu {
let next_mode = if self.pos.line_y >= 144 { let next_mode = if self.pos.line_y >= 144 {
self.interrupt.set_vblank(true); self.interrupt.set_vblank(true);
if self.stat.vblank_intr() { if self.stat.vblank_int() {
self.interrupt.set_lcd_stat(true); self.interrupt.set_lcd_stat(true);
} }
Mode::VBlank Mode::VBlank
} else { } else {
if self.stat.oam_intr() { if self.stat.oam_int() {
self.interrupt.set_lcd_stat(true); self.interrupt.set_lcd_stat(true);
} }
@ -88,7 +88,7 @@ impl Ppu {
self.stat.set_mode(next_mode); self.stat.set_mode(next_mode);
if self.stat.coincidence_intr() { if self.stat.coincidence_int() {
let are_equal = self.pos.line_y == self.pos.ly_compare; let are_equal = self.pos.line_y == self.pos.ly_compare;
self.stat.set_coincidence(are_equal); self.stat.set_coincidence(are_equal);
} }
@ -106,7 +106,7 @@ impl Ppu {
self.pos.line_y = 0; self.pos.line_y = 0;
} }
if self.stat.coincidence_intr() { if self.stat.coincidence_int() {
let are_equal = self.pos.line_y == self.pos.ly_compare; let are_equal = self.pos.line_y == self.pos.ly_compare;
self.stat.set_coincidence(are_equal); self.stat.set_coincidence(are_equal);
} }
@ -214,10 +214,10 @@ impl Interrupt {
bitfield! { bitfield! {
pub struct LCDStatus(u8); pub struct LCDStatus(u8);
impl Debug; impl Debug;
pub coincidence_intr, set_coincidence_intr: 6; pub coincidence_int, set_coincidence_int: 6;
pub oam_intr, set_oam_intr: 5; pub oam_int, set_oam_int: 5;
pub vblank_intr, set_vblank_intr: 4; pub vblank_int, set_vblank_int: 4;
pub hblank_intr, set_hblank_intr: 3; pub hblank_int, set_hblank_int: 3;
pub coincidence, set_coincidence: 2; // LYC == LY Flag pub coincidence, set_coincidence: 2; // LYC == LY Flag
from into Mode, _mode, set_mode: 1, 0; from into Mode, _mode, set_mode: 1, 0;
} }

7
src/timer.rs
View File

@ -21,23 +21,24 @@ impl Timer {
self.divider = self.divider.wrapping_add(1); self.divider = self.divider.wrapping_add(1);
// Get Bit Position // Get Bit Position
let pos = match self.control.speed() { let bit = match self.control.speed() {
Hz4096 => 9, Hz4096 => 9,
Hz262144 => 3, Hz262144 => 3,
Hz65536 => 5, Hz65536 => 5,
Hz16384 => 7, Hz16384 => 7,
}; };
let bit = (self.divider >> pos) as u8 & 0x01; let bit = (self.divider >> bit) as u8 & 0x01;
let timer_enable = self.control.enabled() as u8; let timer_enable = self.control.enabled() as u8;
let and_result = bit & timer_enable; let and_result = bit & timer_enable;
if let Some(previous) = self.prev_and_result { if let Some(previous) = self.prev_and_result {
if previous == 0x01 && and_result == 0x00 { if previous == 0x01 && and_result == 0x00 {
// Falling Edge, increase TIMA Regiser // Falling Edge, increase TIMA Register
self.increment_tima(); self.increment_tima();
} }
} }
self.prev_and_result = Some(and_result); self.prev_and_result = Some(and_result);
} }
} }