fix(cpu): use enums only of maintaining IME register state
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77c7c610d0
commit
748c32c446
30
src/cpu.rs
30
src/cpu.rs
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@ -4,7 +4,6 @@ use super::interrupt::{InterruptEnable, InterruptFlag};
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use super::ppu::Ppu;
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use super::ppu::Ppu;
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use bitfield::bitfield;
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use bitfield::bitfield;
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use std::fmt::{Display, Formatter, Result as FmtResult};
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use std::fmt::{Display, Formatter, Result as FmtResult};
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use std::ops::Add;
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#[derive(Debug, Clone, Default)]
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#[derive(Debug, Clone, Default)]
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pub struct Cpu {
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pub struct Cpu {
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@ -155,13 +154,18 @@ impl Cpu {
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}
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}
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fn check_ime(&mut self) {
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fn check_ime(&mut self) {
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if let ImeState::EnablePending(count) = self.ime {
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match self.ime {
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self.ime = if count < 2 {
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ImeState::Pending => {
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self.ime.wait()
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// This is within the context of the EI instruction, we need to not update EI until the end of the
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} else {
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// next executed Instruction
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ImeState::Enabled
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self.ime = ImeState::PendingEnd;
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}
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ImeState::PendingEnd => {
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// The Instruction after EI has now been executed, so we want to enable the IME flag here
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self.ime = ImeState::Enabled;
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}
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ImeState::Disabled | ImeState::Enabled => {} // Do Nothing
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}
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}
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};
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}
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}
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fn handle_interrupts(&mut self) {
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fn handle_interrupts(&mut self) {
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@ -478,8 +482,9 @@ pub enum HaltState {
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#[derive(Debug, Clone, Copy)]
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#[derive(Debug, Clone, Copy)]
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pub enum ImeState {
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pub enum ImeState {
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Disabled,
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Disabled,
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Pending,
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PendingEnd,
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Enabled,
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Enabled,
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EnablePending(u8),
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}
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}
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impl Default for ImeState {
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impl Default for ImeState {
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@ -487,12 +492,3 @@ impl Default for ImeState {
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Self::Disabled
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Self::Disabled
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}
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}
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}
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}
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impl ImeState {
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pub fn wait(self) -> Self {
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match self {
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Self::EnablePending(count) => Self::EnablePending(count + 1),
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_ => panic!("IME is {:?}, however wait() was called", self),
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}
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}
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}
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@ -1022,7 +1022,7 @@ impl Instruction {
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Instruction::EI => {
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Instruction::EI => {
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// Enable IME (After the next instruction)
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// Enable IME (After the next instruction)
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// FIXME: IME is set after the next instruction, this currently is not represented in this emulator.
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// FIXME: IME is set after the next instruction, this currently is not represented in this emulator.
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cpu.set_ime(ImeState::EnablePending(0));
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cpu.set_ime(ImeState::Pending);
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Cycle::new(4)
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Cycle::new(4)
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}
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}
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Instruction::CALL(cond, nn) => {
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Instruction::CALL(cond, nn) => {
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