chore: update README
This commit is contained in:
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@ -4,10 +4,10 @@
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### Status
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### Status
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* From [Blargg Test ROMs](https://github.com/L-P/blargg-test-roms/)
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* From [Blargg Test ROMs](https://github.com/L-P/blargg-test-roms/)
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* [x] cpu_instrs
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* [x] cpu_instrs
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* [x] instr_timing
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* [ ] instr_timing (kind of)
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* [x] mem_timing
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* [x] mem_timing
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* [x] mem_timing-2
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* [x] mem_timing-2
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* [ ] Partially dmg_sound
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* [ ] dmg_sound (partial)
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* [x] [dmg-acid2](https://github.com/mattcurrie/dmg-acid2)
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* [x] [dmg-acid2](https://github.com/mattcurrie/dmg-acid2)
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* From [mooneye-gb](https://github.com/Gekkio/mooneye-gb):
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* From [mooneye-gb](https://github.com/Gekkio/mooneye-gb):
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* Cartridges:
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* Cartridges:
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@ -16,7 +16,7 @@
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* [x] MBC2
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* [x] MBC2
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* [x] MBC5
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* [x] MBC5
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* Implements a cycle-accurate PPU FIFO
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* Implements a cycle-accurate PPU FIFO
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* Doesn't \*exactly\* work right just yet
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* Doesn't \*exactly\* work just yet
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Supports: ROM-only, MBC1, MBC2, MBC3 and MBC5 games.
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Supports: ROM-only, MBC1, MBC2, MBC3 and MBC5 games.
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@ -73,6 +73,7 @@ impl Bus {
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fn tick(&mut self, limit: u8) {
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fn tick(&mut self, limit: u8) {
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for _ in 0..limit {
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for _ in 0..limit {
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self.timer.tick();
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self.timer.tick();
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self.cart.as_mut().map(|cart| cart.tick());
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self.ppu.tick();
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self.ppu.tick();
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self.apu.tick(self.timer.divider);
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self.apu.tick(self.timer.divider);
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self.dma_tick()
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self.dma_tick()
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188
src/cartridge.rs
188
src/cartridge.rs
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@ -1,4 +1,8 @@
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use bitfield::bitfield;
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use crate::bus::BusIo;
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use crate::bus::BusIo;
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use crate::emu::SM83_CLOCK_SPEED;
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use crate::Cycle;
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const RAM_SIZE_ADDRESS: usize = 0x0149;
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const RAM_SIZE_ADDRESS: usize = 0x0149;
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const ROM_SIZE_ADDRESS: usize = 0x0148;
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const ROM_SIZE_ADDRESS: usize = 0x0148;
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@ -33,6 +37,10 @@ impl Cartridge {
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self.mbc.write_ext_ram(memory)
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self.mbc.write_ext_ram(memory)
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}
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}
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pub(crate) fn tick(&mut self) {
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self.mbc.tick()
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}
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fn detect_mbc(memory: &[u8]) -> Box<dyn MBCIo> {
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fn detect_mbc(memory: &[u8]) -> Box<dyn MBCIo> {
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let ram_size = Self::detect_ram_info(memory);
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let ram_size = Self::detect_ram_info(memory);
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let rom_size = Self::detect_rom_info(memory);
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let rom_size = Self::detect_rom_info(memory);
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@ -281,10 +289,120 @@ impl MBCIo for MBC1 {
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}
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}
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}
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}
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impl RtcTick for MBC1 {
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fn tick(&mut self) {}
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}
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#[derive(Debug, Default, Clone, Copy)]
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struct Rtc {
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/// 6-bit unsigned integer
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sec: u8,
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/// 6-bit unsigned integer
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min: u8,
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/// 6-bit unsigned integer
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hr: u8,
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day_low: u8,
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day_high: DayHigh,
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cycles: Cycle,
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}
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impl Rtc {
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fn inc_day(&mut self) {
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// TODO: Figure out order of operations, the brackets are a bit too defenseive here
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let days: u16 = (((self.day_high.ninth() as u16) << 8) | self.day_low as u16) + 1;
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if days > 0x1FF {
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self.day_high.set_carry(true);
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}
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self.day_high.set_ninth(((days >> 8) & 0x01) == 0x01);
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self.day_low = days as u8;
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}
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}
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impl RtcTick for Rtc {
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fn tick(&mut self) {
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// This is the sort of situation where you'd want to use a scheduler.
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if self.day_high.halt() {
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return;
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}
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self.cycles += 1;
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if self.cycles >= SM83_CLOCK_SPEED {
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self.cycles %= SM83_CLOCK_SPEED;
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self.sec += 1;
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if self.sec == 60 {
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self.sec = 0;
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self.min += 1;
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}
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if self.min == 60 {
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self.min = 0;
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self.hr += 1;
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}
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if self.hr == 24 {
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self.hr = 0;
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self.inc_day();
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}
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}
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}
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}
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trait RtcTick {
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fn tick(&mut self);
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}
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bitfield! {
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struct DayHigh(u8);
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impl Debug;
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_, set_carry: 7;
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halt, _: 6;
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ninth, set_ninth: 0;
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}
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impl Copy for DayHigh {}
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impl Clone for DayHigh {
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fn clone(&self) -> Self {
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*self
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}
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}
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impl Default for DayHigh {
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fn default() -> Self {
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Self(0)
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}
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}
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impl From<u8> for DayHigh {
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fn from(byte: u8) -> Self {
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Self(byte)
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}
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}
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impl From<DayHigh> for u8 {
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fn from(dh: DayHigh) -> Self {
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dh.0
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}
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}
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#[derive(Debug, Clone, Copy)]
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#[derive(Debug, Clone, Copy)]
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enum MBC3Device {
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enum MBC3Device {
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ExternalRam,
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ExternalRam,
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RealTimeClock,
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Rtc(RtcRegister),
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}
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#[derive(Debug, Clone, Copy)]
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enum RtcRegister {
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Second,
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Minute,
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Hour,
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DayLow,
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DayHigh,
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}
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}
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#[derive(Debug)]
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#[derive(Debug)]
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@ -302,6 +420,8 @@ struct MBC3 {
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prev_latch_write: Option<u8>,
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prev_latch_write: Option<u8>,
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has_battery: bool,
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has_battery: bool,
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rtc: Rtc,
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rtc_latch: Option<Rtc>,
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}
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}
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impl MBC3 {
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impl MBC3 {
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mapped: Default::default(),
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mapped: Default::default(),
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prev_latch_write: Default::default(),
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prev_latch_write: Default::default(),
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has_battery: Default::default(),
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has_battery: Default::default(),
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rtc: Default::default(),
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rtc_latch: Default::default(),
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}
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}
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}
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}
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@ -325,6 +447,8 @@ impl MBC3 {
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devs_enabled: Default::default(),
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devs_enabled: Default::default(),
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mapped: Default::default(),
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mapped: Default::default(),
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prev_latch_write: Default::default(),
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prev_latch_write: Default::default(),
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rtc: Default::default(),
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rtc_latch: Default::default(),
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has_battery: true,
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has_battery: true,
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}
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}
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}
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}
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@ -348,6 +472,7 @@ impl Savable for MBC3 {
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impl MBCIo for MBC3 {
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impl MBCIo for MBC3 {
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fn handle_read(&self, addr: u16) -> MBCResult {
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fn handle_read(&self, addr: u16) -> MBCResult {
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use MBCResult::*;
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use MBCResult::*;
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use RtcRegister::*;
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let res = match addr {
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let res = match addr {
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0x0000..=0x3FFF => Address(addr as usize),
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0x0000..=0x3FFF => Address(addr as usize),
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Some(MBC3Device::ExternalRam) if self.devs_enabled => {
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Some(MBC3Device::ExternalRam) if self.devs_enabled => {
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Value(self.memory[0x2000 * self.ram_bank as usize + (addr as usize - 0xA000)])
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Value(self.memory[0x2000 * self.ram_bank as usize + (addr as usize - 0xA000)])
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}
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}
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Some(MBC3Device::RealTimeClock) if self.devs_enabled => {
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Some(MBC3Device::Rtc(rtc_reg)) if self.devs_enabled => Value(match rtc_reg {
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todo!("Return Latched value of register")
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Second => self.rtc_latch.as_ref().map(|rtc| rtc.sec).unwrap_or(0xFF),
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}
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Minute => self.rtc_latch.as_ref().map(|rtc| rtc.min).unwrap_or(0xFF),
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Hour => self.rtc_latch.as_ref().map(|rtc| rtc.hr).unwrap_or(0xFF),
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DayLow => self
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.rtc_latch
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.as_ref()
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.map(|rtc| rtc.day_low)
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.unwrap_or(0xFF),
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DayHigh => self
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.rtc_latch
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.as_ref()
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.map(|rtc| rtc.day_high.into())
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.unwrap_or(0xFF),
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}),
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_ => Value(0xFF),
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_ => Value(0xFF),
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},
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},
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_ => unreachable!("A read from {:#06X} should not be handled by MBC3", addr),
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_ => unreachable!("A read from {:#06X} should not be handled by MBC3", addr),
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}
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}
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fn handle_write(&mut self, addr: u16, byte: u8) {
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fn handle_write(&mut self, addr: u16, byte: u8) {
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use RtcRegister::*;
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match addr {
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match addr {
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0x000..=0x1FFF => self.devs_enabled = (byte & 0x0F) == 0x0A, // Enable External RAM and Access to RTC if there is one
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0x000..=0x1FFF => self.devs_enabled = (byte & 0x0F) == 0x0A, // Enable External RAM and Access to RTC if there is one
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0x2000..=0x3FFF => {
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0x2000..=0x3FFF => {
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self.ram_bank = byte & 0x03;
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self.ram_bank = byte & 0x03;
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self.mapped = Some(MBC3Device::ExternalRam);
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self.mapped = Some(MBC3Device::ExternalRam);
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}
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}
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0x08 | 0x09 | 0x0A | 0x0B | 0x0C => {
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0x08 => self.mapped = Some(MBC3Device::Rtc(Second)),
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self.mapped = Some(MBC3Device::RealTimeClock);
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0x09 => self.mapped = Some(MBC3Device::Rtc(Minute)),
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}
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0x0A => self.mapped = Some(MBC3Device::Rtc(Hour)),
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0x0B => self.mapped = Some(MBC3Device::Rtc(DayLow)),
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0x0C => self.mapped = Some(MBC3Device::Rtc(DayHigh)),
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_ => {}
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_ => {}
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},
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},
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0x6000..=0x7FFF => {
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0x6000..=0x7FFF => {
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if let Some(0x00) = self.prev_latch_write {
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if let Some(0x00) = self.prev_latch_write {
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if byte == 0x01 {
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if byte == 0x01 {
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todo!("Perform Data Latch")
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self.rtc_latch = Some(self.rtc);
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}
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}
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}
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}
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self.prev_latch_write = Some(byte);
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self.prev_latch_write = Some(byte);
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Some(MBC3Device::ExternalRam) if self.devs_enabled => {
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Some(MBC3Device::ExternalRam) if self.devs_enabled => {
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self.memory[0x2000 * self.ram_bank as usize + (addr as usize - 0xA000)] = byte
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self.memory[0x2000 * self.ram_bank as usize + (addr as usize - 0xA000)] = byte
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}
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}
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Some(MBC3Device::RealTimeClock) if self.devs_enabled => {
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Some(MBC3Device::Rtc(rtc_reg)) if self.devs_enabled => match rtc_reg {
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todo!("Write to RTC")
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Second => self.rtc.sec = byte & 0x3F,
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}
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Minute => self.rtc.min = byte & 0x3F,
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Hour => self.rtc.hr = byte & 0x1F,
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DayLow => self.rtc.day_low = byte & 0xFF,
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DayHigh => self.rtc.day_high = (byte & 0xC1).into(),
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},
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_ => {}
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_ => {}
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},
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},
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_ => unreachable!("A write to {:#06X} should not be handled by MBC3", addr),
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_ => unreachable!("A write to {:#06X} should not be handled by MBC3", addr),
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@ -408,6 +554,12 @@ impl MBCIo for MBC3 {
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}
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}
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}
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}
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impl RtcTick for MBC3 {
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fn tick(&mut self) {
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self.rtc.tick();
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}
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}
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#[derive(Debug)]
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#[derive(Debug)]
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struct MBC5 {
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struct MBC5 {
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/// 9-bit number
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/// 9-bit number
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@ -495,6 +647,10 @@ impl MBCIo for MBC5 {
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}
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}
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}
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}
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impl RtcTick for MBC5 {
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fn tick(&mut self) {}
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}
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#[derive(Debug)]
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#[derive(Debug)]
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struct MBC2 {
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struct MBC2 {
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/// 4-bit number
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/// 4-bit number
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}
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}
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}
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}
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impl RtcTick for MBC2 {
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fn tick(&mut self) {}
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}
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#[derive(Debug)]
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#[derive(Debug)]
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struct NoMBC;
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struct NoMBC;
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@ -606,7 +766,11 @@ impl MBCIo for NoMBC {
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}
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}
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}
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}
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trait MBCIo: Savable {
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impl RtcTick for NoMBC {
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fn tick(&mut self) {}
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}
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trait MBCIo: Savable + RtcTick {
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fn handle_read(&self, addr: u16) -> MBCResult;
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fn handle_read(&self, addr: u16) -> MBCResult;
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fn handle_write(&mut self, addr: u16, byte: u8);
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fn handle_write(&mut self, addr: u16, byte: u8);
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}
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}
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