chore: change how bus components are clocked

src/bus.rs

@@ -67,23 +67,19 @@ impl Bus {
         self.cartridge.as_ref()?.title()
     }
 
-    pub(crate) fn step(&mut self, cycles: Cycle) {
+    pub(crate) fn clock(&mut self) {
-        self.step_dma(cycles);
+        self.ppu.clock();
-        self.ppu.step(cycles);
+        self.timer.clock();
-        self.timer.step(cycles);
+        self.sound.clock();
-        self.sound.step(cycles);
+        self.clock_dma();
     }
 
-    pub(crate) fn step_dma(&mut self, pending: Cycle) {
+    fn clock_dma(&mut self) {
-        let pending_cycles: u32 = pending.into();
-
-        for _ in 0..pending_cycles {
         if let Some((src_addr, dest_addr)) = self.ppu.dma.clock() {
             let byte = self.oam_read_byte(src_addr);
             self.oam_write_byte(dest_addr, byte);
         }
     }
-    }
 
     pub(crate) fn timer(&self) -> Timer {
         self.timer

src/cpu.rs

@@ -136,8 +136,10 @@ impl Cpu {
             }
         };
 
-        self.bus.step(cycles);
+        let pending: u32 = cycles.into();
-        self.bus.step_dma(cycles);
+        for _ in 0..pending {
+            self.bus.clock();
+        }
 
         self.handle_interrupts();
 

src/ppu.rs

@@ -66,11 +66,7 @@ impl BusIo for Ppu {
 }
 
 impl Ppu {
-    pub(crate) fn step(&mut self, cycles: Cycle) {
+    pub(crate) fn clock(&mut self) {
-        let start: u32 = self.cycle.into();
-        let end: u32 = cycles.into();
-
-        for _ in start..(start + end) {
         self.cycle += 1;
 
         match self.stat.mode() {
@@ -188,7 +184,6 @@ impl Ppu {
             }
         }
     }
-    }
 
     fn scan_oam(&mut self) {
         if self.scan_state.mode() == OamScanMode::Scan {

src/sound.rs

@@ -7,7 +7,7 @@ pub(crate) struct Sound {
 }
 
 impl Sound {
-    pub(crate) fn step(&mut self, _cycles: Cycle) {
+    pub(crate) fn clock(&mut self) {
         //
     }
 }

src/timer.rs

@@ -16,10 +16,9 @@ pub(crate) struct Timer {
 }
 
 impl Timer {
-    pub(crate) fn step(&mut self, cycles: Cycle) {
+    pub(crate) fn clock(&mut self) {
         use TimerSpeed::*;
 
-        for _ in 0..cycles.into() {
         self.divider = self.divider.wrapping_add(1);
 
         // Get Bit Position
@@ -43,7 +42,6 @@ impl Timer {
 
         self.prev_and_result = Some(and_result);
     }
-    }
 
     fn increment_tima(&mut self) {
         let (result, did_overflow) = self.counter.overflowing_add(1);