feat(bus): implement echo RAM
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2733bbe6d7
commit
41081e9cce
28
src/bus.rs
28
src/bus.rs
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@ -110,7 +110,19 @@ impl Bus {
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}
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}
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0xE000..=0xFDFF => {
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0xE000..=0xFDFF => {
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// Mirror of 0xC000 to 0xDDFF
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// Mirror of 0xC000 to 0xDDFF
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unimplemented!("Unable to read {:#06X} in Restricted Mirror", addr);
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// ECHO RAM
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match addr {
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0xE000..=0xEFFF => {
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// 4KB Work RAM Bank 0
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self.wram.read_byte(addr)
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}
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0xF000..=0xFDFF => {
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// 4KB Work RAM Bank 1 -> N
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self.vwram.read_byte(addr)
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}
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_ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
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}
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}
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}
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0xFE00..=0xFE9F => {
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0xFE00..=0xFE9F => {
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// Sprite Attribute Table
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// Sprite Attribute Table
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@ -200,7 +212,19 @@ impl Bus {
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}
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}
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0xE000..=0xFDFF => {
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0xE000..=0xFDFF => {
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// Mirror of 0xC000 to 0xDDFF
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// Mirror of 0xC000 to 0xDDFF
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unimplemented!("Unable to write to {:#06X} in Restricted Mirror", addr);
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// ECHO RAM
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match addr {
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0xE000..=0xEFFF => {
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// 4KB Work RAM Bank 0
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self.wram.write_byte(addr, byte);
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}
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0xF000..=0xFDFF => {
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// 4KB Work RAM Bank 1 -> N
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self.vwram.write_byte(addr, byte);
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}
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_ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
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}
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}
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}
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0xFE00..=0xFE9F => {
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0xFE00..=0xFE9F => {
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// Sprite Attribute Table
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// Sprite Attribute Table
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