chore: improve unreachable! and panic! error messages
This commit is contained in:
parent
2813b762dd
commit
342e6616ac
12
src/bus.rs
12
src/bus.rs
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@ -102,7 +102,7 @@ impl Bus {
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0xA000..=0xBFFF => match self.cartridge.as_ref() {
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// 8KB External RAM
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Some(cart) => cart.read_byte(addr),
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None => panic!("Tried to read from the external RAM of a non-existent cartridge"),
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None => panic!("Tried to read from a non-existent cartridge"),
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},
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0xC000..=0xCFFF => {
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// 4KB Work RAM Bank 0
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@ -120,7 +120,7 @@ impl Bus {
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// Sprite Attribute Table
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unimplemented!("Unable to read {:#06X} in the Sprite Attribute Table", addr);
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}
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0xFEA0..=0xFEFF => unreachable!("{:#06X} is not allowed to be used", addr),
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0xFEA0..=0xFEFF => unreachable!("{:#06X} is not allowed to be read from", addr),
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0xFF00..=0xFF7F => {
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// IO Registers
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match addr {
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@ -169,14 +169,14 @@ impl Bus {
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// 16KB ROM bank 00
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match self.cartridge.as_mut() {
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Some(cart) => cart.write_byte(addr, byte),
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None => panic!("Tried to write into non-existent Cartridge"),
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None => panic!("Tried to write into non-existent cartridge"),
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}
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}
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0x4000..=0x7FFF => {
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// 16KB ROM Bank 01 -> NN (switchable via MB)
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match self.cartridge.as_mut() {
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Some(cart) => cart.write_byte(addr, byte),
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None => panic!("Tried to write into non-existent Cartridge"),
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None => panic!("Tried to write into non-existent cartridge"),
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}
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}
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0x8000..=0x9FFF => {
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@ -187,7 +187,7 @@ impl Bus {
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// 8KB External RAM
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match self.cartridge.as_mut() {
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Some(cart) => cart.write_byte(addr, byte),
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None => panic!("Tried to write into non-existent Cartridge"),
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None => panic!("Tried to write into non-existent cartridge"),
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}
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}
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0xC000..=0xCFFF => {
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@ -206,7 +206,7 @@ impl Bus {
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// Sprite Attribute Table
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unimplemented!("Unable to write to {:#06X} in Sprite Attribute Table", addr);
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}
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0xFEA0..=0xFEFF => unreachable!("{:#06X} is not allowed to be used", addr),
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0xFEA0..=0xFEFF => unreachable!("{:#06X} is not allowed to be written to", addr),
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0xFF00..=0xFF7F => {
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// IO Registers
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match addr {
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@ -62,7 +62,7 @@ impl Cartridge {
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0x00 => MBCKind::None,
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0x01 => MBCKind::MBC1,
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0x19 => MBCKind::MBC5,
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_ => panic!("Cartridge uses an unknown Memory Bank Controller"),
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_ => unimplemented!("{} is the id of an unsupported memory bank controller", id),
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}
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}
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}
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@ -107,7 +107,7 @@ impl MBC1 {
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ThirtyTwo | Sixteen | Eight | Four => 0,
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SixtyFour => (self.ram_bank & 0x01) << 5,
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OneHundredTwentyEight => self.ram_bank << 5,
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_ => unreachable!("{:#?} is not a valid MBC1 BankCount", self.bank_count),
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_ => unreachable!("{:?} is not a valid MBC1 BankCount", self.bank_count),
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}
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}
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@ -126,13 +126,15 @@ impl MBC1 {
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num &= !(0x03 << 5);
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num | ((self.ram_bank) << 5)
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}
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_ => unreachable!("{:#?} is not a valid MBC1 BankCount", self.bank_count),
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_ => unreachable!("{:?} is not a valid MBC1 BankCount", self.bank_count),
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}
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}
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fn apply_rom_size_bitmask(&self, byte: u8) -> u8 {
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use BankCount::*;
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let err_bc = self.bank_count; // Bank Count, but with a shorter name
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match self.bank_count {
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Four => byte & 0b00000011,
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Eight => byte & 0b00000111,
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@ -140,7 +142,7 @@ impl MBC1 {
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ThirtyTwo => byte & 0b00011111,
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SixtyFour => byte & 0b00011111,
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OneHundredTwentyEight => byte & 0b00011111,
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_ => unreachable!("{:#?} does not have a bitmask in MBC1", self.bank_count),
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_ => unreachable!("{:?} does not have a rom size bitmask in MBC1", err_bc),
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}
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}
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@ -292,7 +294,7 @@ impl From<u8> for RamSize {
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0x03 => _32KB,
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0x04 => _128KB,
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0x05 => _64KB,
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_ => unreachable!("{:#04X} is an invalid value for RAMSize"),
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_ => unreachable!("{:#04X} is not a valid value for RAMSize", byte),
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}
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}
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}
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@ -358,7 +360,7 @@ impl From<u8> for BankCount {
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0x52 => SeventyTwo,
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0x53 => Eighty,
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0x54 => NinetySix,
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_ => unreachable!("{:#04X} is an invalid value for BankCount", byte),
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_ => unreachable!("{:#04X} is not a valid value for BankCount", byte),
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}
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}
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}
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@ -137,7 +137,7 @@ impl Instruction {
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| RegisterPair::DE
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| RegisterPair::HL
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| RegisterPair::SP => cpu.set_register_pair(pair, nn),
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_ => unreachable!(),
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_ => unreachable!("There is no \"LD {:?}, nn\" instruction", pair),
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}
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Cycles::new(12)
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}
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@ -164,7 +164,7 @@ impl Instruction {
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cpu.set_register_pair(RegisterPair::HL, addr - 1);
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"LD ({:?}), A\" instruction", pair),
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}
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Cycles::new(8)
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}
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@ -193,7 +193,7 @@ impl Instruction {
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cpu.set_register_pair(RegisterPair::HL, addr - 1);
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"LD A, ({:?})\" instruction", pair),
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}
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Cycles::new(8)
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}
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@ -294,7 +294,7 @@ impl Instruction {
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cpu.set_register(Register::A, byte);
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Cycles::new(16)
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"LD {:?}, {:?}\" instruction", lhs, rhs),
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},
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Instruction::STOP => Cycles::new(4),
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Instruction::JR(cond, offset) => {
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@ -356,7 +356,7 @@ impl Instruction {
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cpu.set_register_pair(RegisterPair::HL, sum);
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"ADD HL, {:?}\" instruction", pair),
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}
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cpu.set_flags(flags);
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Cycles::new(8)
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@ -402,7 +402,7 @@ impl Instruction {
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cpu.set_flags(flags);
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Cycles::new(8)
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"ADD {:?}, {:?}\" instruction", lhs, rhs),
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},
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Instruction::INC(registers) => {
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match registers {
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@ -445,7 +445,7 @@ impl Instruction {
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let value = cpu.register_pair(pair);
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cpu.set_register_pair(pair, value + 1);
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"INC {:?}\" instruction", pair),
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}
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Cycles::new(8)
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}
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@ -458,7 +458,7 @@ impl Instruction {
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let value = cpu.register_pair(pair);
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cpu.set_register_pair(pair, value - 1);
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"DEC {:?}\" instruction", pair),
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}
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Cycles::new(8)
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}
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@ -618,7 +618,7 @@ impl Instruction {
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cpu.set_register(Register::A, sum);
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Cycles::new(8)
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"ADC {:?}\" instruction", target),
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},
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Instruction::SUB(target) => match target {
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MATHTarget::Register(reg) => {
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@ -660,7 +660,7 @@ impl Instruction {
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cpu.set_register(Register::A, diff);
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Cycles::new(8)
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"SUB {:?}\" instruction", target),
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},
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Instruction::SBC(target) => match target {
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MATHTarget::Register(reg) => {
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@ -705,7 +705,7 @@ impl Instruction {
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cpu.set_register(Register::A, diff);
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Cycles::new(8)
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"SBC {:?}\" instruction", target),
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},
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Instruction::AND(target) => match target {
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MATHTarget::Register(reg) => {
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@ -749,7 +749,7 @@ impl Instruction {
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cpu.set_register(Register::A, result);
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Cycles::new(8)
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"AND {:?}\" instruction", target),
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},
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Instruction::XOR(target) => match target {
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MATHTarget::Register(reg) => {
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@ -793,7 +793,7 @@ impl Instruction {
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cpu.set_register(Register::A, result);
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Cycles::new(8)
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"XOR {:?}\" instruction", target),
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},
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Instruction::OR(target) => match target {
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MATHTarget::Register(reg) => {
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@ -837,7 +837,7 @@ impl Instruction {
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cpu.set_register(Register::A, result);
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Cycles::new(8)
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"OR {:?}\" instruction", target),
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},
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Instruction::CP(target) => match target {
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MATHTarget::Register(reg) => {
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@ -875,7 +875,7 @@ impl Instruction {
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cpu.set_flags(flags);
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Cycles::new(8)
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"CP {:?}\" instruction", target),
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},
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Instruction::RET(cond) => {
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// RET cc[y] | Essentially a POP PC, Return from Subroutine
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@ -931,14 +931,14 @@ impl Instruction {
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Cycles::new(12)
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}
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Instruction::POP(pair) => {
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// POP rp2[p] | Pop from stack into register pair rp[2]
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// POP rp2[p] | Pop from stack into register pair rp2[]
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// Flags are set when we call cpu.set_register_pair(RegisterPair::AF, value);
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match pair {
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RegisterPair::BC | RegisterPair::DE | RegisterPair::HL | RegisterPair::AF => {
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let value = Self::pop(cpu);
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cpu.set_register_pair(pair, value);
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"POP {:?}\" instruction", pair),
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}
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Cycles::new(12)
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}
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@ -995,7 +995,7 @@ impl Instruction {
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}
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}
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"JP {:?}\" instruction", target),
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},
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Instruction::DI => {
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// Disable IME
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@ -1061,7 +1061,7 @@ impl Instruction {
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let value = cpu.register_pair(pair);
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Self::push(cpu, value);
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}
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_ => unreachable!(),
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_ => unreachable!("There is no \"PUSH {:?}\" instruction", pair),
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}
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Cycles::new(16)
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}
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@ -1814,22 +1814,22 @@ impl Instruction {
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JumpCondition::Always,
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JPTarget::ImmediateWord(cpu.read_imm_word(pc)),
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),
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(3, 3, _, 1, _) => unreachable!("This is the 0xCB Prefix"),
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// (3, 3, _, 2, _) => unreachable!(), ("removed" in documentation)
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// (3, 3, _, 3, _) => unreachable!(), ("removed" in documentation)
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// (3, 3, _, 4, _) => unreachable!(), ("removed" in documentation)
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// (3, 3, _, 5, _) => unreachable!(), ("removed" in documentation)
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(3, 3, _, 1, _) => unreachable!("0xCB is handled by Instruction::from_prefixed_byte"),
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// (3, 3, _, 2, _) => unreachable!("\"removed\" in documentation"),
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// (3, 3, _, 3, _) => unreachable!("\"removed\" in documentation"),
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// (3, 3, _, 4, _) => unreachable!("\"removed\" in documentation"),
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// (3, 3, _, 5, _) => unreachable!("\"removed\" in documentation"),
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(3, 3, _, 6, _) => Self::DI,
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(3, 3, _, 7, _) => Self::EI,
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(3, 4, _, 0..=3, _) => Self::CALL(Table::cc(y), cpu.read_imm_word(pc)), // CALL cc[y], nn
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// (3, 4, _, 4..=7, _) => unreachable!(), ("removed" in documentation)
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// (3, 4, _, 4..=7, _) => unreachable!("\"removed\" in documentation"),
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(3, 5, 0, _, _) => Self::PUSH(Table::rp2(p)), // PUSH rp2[p]
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(3, 5, 1, _, 0) => Self::CALL(JumpCondition::Always, cpu.read_imm_word(pc)), // CALL nn
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// (3, 5, 1, _, 1..=3) => unreachable!(), ("removed" in documentation)
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// (3, 5, 1, _, 1..=3) => unreachable!("\"removed\" in documentation"),
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(3, 6, _, _, _) => Table::x3_alu(y, cpu.read_imm_byte(pc)),
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(3, 7, _, _, _) => Self::RST(y * 8), // RST n
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_ => panic!(
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"Unknown Opcode: {:#x?}\n x: {}, z: {}, q: {}, y: {}, p: {}",
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_ => unreachable!(
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"Unknown Opcode: {:#04X}\n x: {}, z: {}, q: {}, y: {}, p: {}",
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opcode, x, z, q, y, p
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),
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}
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@ -1851,8 +1851,8 @@ impl Instruction {
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1 => Self::BIT(y, Table::r(z)), // BIT y, r[z]
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2 => Self::RES(y, Table::r(z)), // RES y, r[z]
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3 => Self::SET(y, Table::r(z)), // SET y, r[z]
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_ => panic!(
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"Unknown Prefixed Opcode: 0xCB {:#x?}\n x: {}, z: {}, q: {}, y: {}, p: {}",
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_ => unreachable!(
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"Unknown Prefixed Opcode: 0xCB {:#04X}\n x: {}, z: {}, q: {}, y: {}, p: {}",
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opcode, x, z, q, y, p
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),
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}
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