chore: reorganize instructions.rs

This commit is contained in:
Rekai Nyangadzayi Musuka 2020-12-23 01:17:13 -06:00
parent 9cd4c4ea11
commit 2e1c97e5d7
1 changed files with 70 additions and 69 deletions

View File

@ -1,5 +1,6 @@
use super::cpu::{Cpu, Flags, Register, RegisterPair}; use super::cpu::{Cpu, Flags, Register, RegisterPair};
use std::convert::TryFrom; use std::convert::TryFrom;
#[derive(Debug, Copy, Clone)] #[derive(Debug, Copy, Clone)]
pub enum Instruction { pub enum Instruction {
NOP, NOP,
@ -48,6 +49,75 @@ pub enum Instruction {
SET(u8, InstrRegister), SET(u8, InstrRegister),
} }
#[derive(Debug, Copy, Clone)]
pub enum JPTarget {
RegisterPair(RegisterPair),
ImmediateWord(u16),
}
#[derive(Debug, Copy, Clone)]
pub enum Registers {
Byte(InstrRegister),
Word(RegisterPair),
}
#[derive(Debug, Copy, Clone)]
pub enum MATHTarget {
HL,
SP,
Register(InstrRegister),
RegisterPair(RegisterPair),
ImmediateByte(u8),
}
#[derive(Debug, Copy, Clone)]
pub enum LDTarget {
Register(InstrRegister),
IndirectRegister(InstrRegisterPair),
ByteAtAddress(u16),
ImmediateWord(u16),
ImmediateByte(u8),
RegisterPair(RegisterPair),
ByteAtAddressWithOffset(u8),
}
#[derive(Debug, Copy, Clone)]
enum InstrRegisterPair {
AF,
BC,
DE,
HL,
SP,
PC,
IncrementHL,
DecrementHL,
}
#[derive(Debug, Copy, Clone)]
enum InstrRegister {
A,
B,
C,
D,
E,
H,
L,
IndirectHL, // (HL)
IndirectC, // (0xFF00 + C)
}
#[derive(Debug, Copy, Clone)]
pub enum JumpCondition {
NotZero,
Zero,
NotCarry,
Carry,
Always,
}
#[derive(Debug, Copy, Clone)]
struct Table;
#[derive(Debug, Copy, Clone)] #[derive(Debug, Copy, Clone)]
pub struct Cycles(u8); pub struct Cycles(u8);
@ -1783,50 +1853,6 @@ impl Instruction {
} }
} }
#[derive(Debug, Copy, Clone)]
pub enum JPTarget {
RegisterPair(RegisterPair),
ImmediateWord(u16),
}
#[derive(Debug, Copy, Clone)]
pub enum Registers {
Byte(InstrRegister),
Word(RegisterPair),
}
#[derive(Debug, Copy, Clone)]
pub enum MATHTarget {
HL,
SP,
Register(InstrRegister),
RegisterPair(RegisterPair),
ImmediateByte(u8),
}
#[derive(Debug, Copy, Clone)]
pub enum LDTarget {
Register(InstrRegister),
IndirectRegister(InstrRegisterPair),
ByteAtAddress(u16),
ImmediateWord(u16),
ImmediateByte(u8),
RegisterPair(RegisterPair),
ByteAtAddressWithOffset(u8),
}
#[derive(Debug, Copy, Clone)]
enum InstrRegisterPair {
AF,
BC,
DE,
HL,
SP,
PC,
IncrementHL,
DecrementHL,
}
impl From<RegisterPair> for InstrRegisterPair { impl From<RegisterPair> for InstrRegisterPair {
fn from(pair: RegisterPair) -> Self { fn from(pair: RegisterPair) -> Self {
match pair { match pair {
@ -1861,19 +1887,6 @@ impl TryFrom<InstrRegisterPair> for RegisterPair {
} }
} }
#[derive(Debug, Copy, Clone)]
enum InstrRegister {
A,
B,
C,
D,
E,
H,
L,
IndirectHL, // (HL)
IndirectC, // (0xFF00 + C)
}
impl TryFrom<Register> for InstrRegister { impl TryFrom<Register> for InstrRegister {
type Error = &'static str; // FIXME: Proper error type goes here type Error = &'static str; // FIXME: Proper error type goes here
@ -1913,18 +1926,6 @@ impl TryFrom<InstrRegister> for Register {
} }
} }
#[derive(Debug, Copy, Clone)]
pub enum JumpCondition {
NotZero,
Zero,
NotCarry,
Carry,
Always,
}
#[derive(Debug, Copy, Clone)]
struct Table;
impl Table { impl Table {
pub fn r(index: u8) -> InstrRegister { pub fn r(index: u8) -> InstrRegister {
match index { match index {