fix(cpu): Ensure mask the high bits of the flag register

There was a bug where POP AF returned 0x1301. In this example, the A
register would be set to 0x13, and the Flag register woud be set to
0x01, which is an invalid state considering only bits 4 -> 7 of the flag
register are used. This commit masks the flag register with & 0xF0
whenever it is read or written to so that we can ensure that only the
high bits can ever be potentially set

src/cpu.rs

@@ -441,13 +441,13 @@ impl Display for Flags {
 
 impl From<Flags> for u8 {
     fn from(flags: Flags) -> Self {
-        flags.0
+        flags.0 & 0xF0
     }
 }
 
 impl From<u8> for Flags {
     fn from(byte: u8) -> Self {
-        Self(byte)
+        Self(byte & 0xF0)
     }
 }